Searched +full:0 +full:x1b4 (Results 1 – 25 of 232) sorted by relevance
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14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
14 #define CODA_REG_BIT_CODE_RUN 0x00015 #define CODA_REG_RUN_ENABLE (1 << 0)16 #define CODA_REG_BIT_CODE_DOWN 0x00417 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)19 #define CODA_REG_BIT_HOST_IN_REQ 0x00820 #define CODA_REG_BIT_INT_CLEAR 0x00c21 #define CODA_REG_BIT_INT_CLEAR_SET 0x122 #define CODA_REG_BIT_INT_STATUS 0x01023 #define CODA_REG_BIT_CODE_RESET 0x014[all …]
6 #define LB_AON_EMMC_CFG_REG0 0x1B07 #define LB_AON_EMMC_CFG_REG1 0x1B48 #define LB_AON_EMMC_CFG_REG2 0x1B811 #define PARA_DLL_START(x) ((x) & 0xFF)12 #define PARA_DLL_START_MASK 0xFF22 #define READ_DQS_DELAY(x) ((x) & 0x7F)23 #define READ_DQS_DELAY_MASK (0x7F)25 #define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8)26 #define CLK_SAMP_DELAY_MASK (0x7F << 8)
42 efuse: efuse@0 {44 reg = <0x0 0x2000>;51 reg = <0x1b4 0x6>;55 reg = <0x1f4 0x4>;
10 #define QSERDES_PLL_BG_TIMER 0x00c11 #define QSERDES_PLL_SSC_PER1 0x01c12 #define QSERDES_PLL_SSC_PER2 0x02013 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x02414 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x02815 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x03017 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c18 #define QSERDES_PLL_CLK_ENABLE1 0x04019 #define QSERDES_PLL_SYS_CLK_CTRL 0x044[all …]
11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x0012 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x0413 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x1014 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x1415 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x1816 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x2018 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x2419 #define QSERDES_V6_COM_DEC_START_MODE1 0x2820 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c[all …]
10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x3011 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x3412 #define QSERDES_V5_20_TX_LANE_MODE_1 0x7813 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x8015 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x9016 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb017 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x00821 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c[all …]
10 #define QSERDES_V5_COM_ATB_SEL1 0x00011 #define QSERDES_V5_COM_ATB_SEL2 0x00412 #define QSERDES_V5_COM_FREQ_UPDATE 0x00813 #define QSERDES_V5_COM_BG_TIMER 0x00c14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x01015 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x01416 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x01817 #define QSERDES_V5_COM_SSC_PER1 0x01c18 #define QSERDES_V5_COM_SSC_PER2 0x02019 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024[all …]
10 #define QSERDES_V4_COM_ATB_SEL1 0x00011 #define QSERDES_V4_COM_ATB_SEL2 0x00412 #define QSERDES_V4_COM_FREQ_UPDATE 0x00813 #define QSERDES_V4_COM_BG_TIMER 0x00c14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x01015 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x01416 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x01817 #define QSERDES_V4_COM_SSC_PER1 0x01c18 #define QSERDES_V4_COM_SSC_PER2 0x02019 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024[all …]
10 #define QPHY_V3_PCS_SW_RESET 0x00011 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x00412 #define QPHY_V3_PCS_START_CONTROL 0x00813 #define QPHY_V3_PCS_TXMGN_V0 0x00c14 #define QPHY_V3_PCS_TXMGN_V1 0x01015 #define QPHY_V3_PCS_TXMGN_V2 0x01416 #define QPHY_V3_PCS_TXMGN_V3 0x01817 #define QPHY_V3_PCS_TXMGN_V4 0x01c18 #define QPHY_V3_PCS_TXMGN_LS 0x02019 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024[all …]
10 #define QSERDES_COM_ATB_SEL1 0x00011 #define QSERDES_COM_ATB_SEL2 0x00412 #define QSERDES_COM_FREQ_UPDATE 0x00813 #define QSERDES_COM_BG_TIMER 0x00c14 #define QSERDES_COM_SSC_EN_CENTER 0x01015 #define QSERDES_COM_SSC_ADJ_PER1 0x01416 #define QSERDES_COM_SSC_ADJ_PER2 0x01817 #define QSERDES_COM_SSC_PER1 0x01c18 #define QSERDES_COM_SSC_PER2 0x02019 #define QSERDES_COM_SSC_STEP_SIZE1 0x024[all …]
10 #define QPHY_V4_PCS_SW_RESET 0x00011 #define QPHY_V4_PCS_REVISION_ID0 0x00412 #define QPHY_V4_PCS_REVISION_ID1 0x00813 #define QPHY_V4_PCS_REVISION_ID2 0x00c14 #define QPHY_V4_PCS_REVISION_ID3 0x01015 #define QPHY_V4_PCS_PCS_STATUS1 0x01416 #define QPHY_V4_PCS_PCS_STATUS2 0x01817 #define QPHY_V4_PCS_PCS_STATUS3 0x01c18 #define QPHY_V4_PCS_PCS_STATUS4 0x02019 #define QPHY_V4_PCS_PCS_STATUS5 0x024[all …]
16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x00017 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x00019 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x00020 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x00021 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x00023 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x00024 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x00025 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x00026 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x00028 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000[all …]
10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))13 #define DPLL1_TOD_CNFG 0x13414 #define DPLL2_TOD_CNFG 0x1B416 #define DPLL1_TOD_STS 0x10B17 #define DPLL2_TOD_STS 0x18B19 #define DPLL1_TOD_TRIGGER 0x11520 #define DPLL2_TOD_TRIGGER 0x19522 #define DPLL1_OPERATING_MODE_CNFG 0x12023 #define DPLL2_OPERATING_MODE_CNFG 0x1A025 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C[all …]
13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x014 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x015 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x016 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x017 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x018 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x019 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x020 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x021 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x022 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0[all …]
14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…[all …]
14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x015 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x316 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x017 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x318 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x019 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x020 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x021 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x022 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x023 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0[all …]
12 #define ANSEL_REG 0x0013 #define TRIS_REG 0x1014 #define PORT_REG 0x2015 #define LAT_REG 0x3016 #define ODCU_REG 0x4017 #define CNPU_REG 0x5018 #define CNPD_REG 0x6019 #define CNCON_REG 0x7020 #define CNEN_REG 0x8021 #define CNSTAT_REG 0x90[all …]