Searched +full:0 +full:x1c00 (Results 1 – 25 of 397) sorted by relevance
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-ar7/ |
| D | ar7.h | 16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
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| /kernel/linux/linux-6.6/arch/mips/include/asm/mach-ar7/ |
| D | ar7.h | 16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/ |
| D | rpmh-rsc.txt | 52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92 register offsets for DRV2 start at 0D00, the register calculations are like
94 DRV0: 0x179C0000
95 DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96 DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97 TCS-OFFSET: 0xD00
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
[all …]
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| /kernel/linux/linux-5.10/drivers/hwtracing/intel_th/ |
| D | pti.h | 12 REG_PTI_CTL = 0x1c00,
15 #define PTI_EN BIT(0)
17 #define PTI_MODE 0xf0
20 #define PTI_CLKDIV 0x000f0000
21 #define PTI_PATGENMODE 0x00f00000
26 #define LPP_DEST_PTI BIT(0)
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| /kernel/linux/linux-6.6/drivers/hwtracing/intel_th/ |
| D | pti.h | 12 REG_PTI_CTL = 0x1c00,
15 #define PTI_EN BIT(0)
17 #define PTI_MODE 0xf0
20 #define PTI_CLKDIV 0x000f0000
21 #define PTI_PATGENMODE 0x00f00000
26 #define LPP_DEST_PTI BIT(0)
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | ep88xc.dts | 19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/ |
| D | ep88xc.dts | 19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fsi/ |
| D | ibm,fsi2spi.yaml | 37 reg = <0x1c00 0x400>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fsi/ |
| D | ibm,fsi2spi.yaml | 38 reg = <0x1c00 0x400>;
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| /kernel/linux/linux-6.6/arch/riscv/include/asm/ |
| D | kvm_aia_aplic.h | 14 #define APLIC_DOMAINCFG 0x0000
15 #define APLIC_DOMAINCFG_RDONLY 0x80000000
18 #define APLIC_DOMAINCFG_BE BIT(0)
20 #define APLIC_SOURCECFG_BASE 0x0004
22 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
23 #define APLIC_SOURCECFG_SM_MASK 0x00000007
24 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
25 #define APLIC_SOURCECFG_SM_DETACH 0x1
26 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
27 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | prm54xx.h | 24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
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| D | prm7xx.h | 26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
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| /kernel/linux/linux-6.6/drivers/bus/ |
| D | omap_l3_smx.h | 14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
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| /kernel/linux/linux-5.10/drivers/bus/ |
| D | omap_l3_smx.h | 14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
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| /kernel/linux/linux-6.6/sound/pci/ctxfi/ |
| D | ctmixer.h | 20 #define INIT_VOL 0x1c00
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| /kernel/linux/linux-5.10/sound/pci/ctxfi/ |
| D | ctmixer.h | 20 #define INIT_VOL 0x1c00
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ |
| D | ga102.c | 31 .addr2 = 0x1c00,
47 return 0; in ga102_nvdec_nofw()
60 return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec); in ga102_nvdec_new()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,rpmh-rsc.yaml | 78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
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| /kernel/linux/linux-6.6/drivers/mfd/ |
| D | timberdale.h | 23 #define TIMB_REV_MAJOR 0x00
24 #define TIMB_REV_MINOR 0x04
25 #define TIMB_HW_CONFIG 0x08
26 #define TIMB_SW_RST 0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
31 #define TIMB_HW_VER_MASK 0x0f
32 #define TIMB_HW_VER0 0x00
33 #define TIMB_HW_VER1 0x01
34 #define TIMB_HW_VER2 0x02
35 #define TIMB_HW_VER3 0x03
[all …]
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | timberdale.h | 23 #define TIMB_REV_MAJOR 0x00
24 #define TIMB_REV_MINOR 0x04
25 #define TIMB_HW_CONFIG 0x08
26 #define TIMB_SW_RST 0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
31 #define TIMB_HW_VER_MASK 0x0f
32 #define TIMB_HW_VER0 0x00
33 #define TIMB_HW_VER1 0x01
34 #define TIMB_HW_VER2 0x02
35 #define TIMB_HW_VER3 0x03
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/renesas/rcar-vin/ |
| D | rcar-csi2.c | 31 #define TREF_REG 0x00
32 #define TREF_TREF BIT(0)
35 #define SRST_REG 0x04
36 #define SRST_SRST BIT(0)
39 #define PHYCNT_REG 0x08
46 #define PHYCNT_ENABLE_0 BIT(0)
49 #define CHKSUM_REG 0x0c
51 #define CHKSUM_CRC_EN BIT(0)
55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
[all …]
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | altera_edac.h | 15 #define CV_CTLCFG_OFST 0x00
18 #define CV_CTLCFG_ECC_EN 0x400
19 #define CV_CTLCFG_ECC_CORR_EN 0x800
20 #define CV_CTLCFG_GEN_SB_ERR 0x2000
21 #define CV_CTLCFG_GEN_DB_ERR 0x4000
26 #define CV_DRAMADDRW_OFST 0x2C
29 #define DRAMADDRW_COLBIT_MASK 0x001F
30 #define DRAMADDRW_COLBIT_SHIFT 0
31 #define DRAMADDRW_ROWBIT_MASK 0x03E0
33 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
[all …]
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| /kernel/linux/linux-6.6/drivers/edac/ |
| D | altera_edac.h | 15 #define CV_CTLCFG_OFST 0x00
18 #define CV_CTLCFG_ECC_EN 0x400
19 #define CV_CTLCFG_ECC_CORR_EN 0x800
20 #define CV_CTLCFG_GEN_SB_ERR 0x2000
21 #define CV_CTLCFG_GEN_DB_ERR 0x4000
26 #define CV_DRAMADDRW_OFST 0x2C
29 #define DRAMADDRW_COLBIT_MASK 0x001F
30 #define DRAMADDRW_COLBIT_SHIFT 0
31 #define DRAMADDRW_ROWBIT_MASK 0x03E0
33 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
[all …]
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| /kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| D | dcore0_tpc0_eml_spmu_regs.h | 23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | tonga_baco.c | 41 { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
42 { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
43 { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
44 { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
45 { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
46 { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
47 { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
48 { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
49 { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
50 { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
[all …]
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