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/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mm-mx8menlo.dts22 pinctrl-0 = <&pinctrl_led>;
40 pinctrl-0 = <&pinctrl_beeper>;
47 #clock-cells = <0>;
54 #size-cells = <0>;
56 pinctrl-0 = <&pinctrl_ecspi1>;
61 canfd: can@0 {
66 reg = <0>;
73 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
77 spidev@0 {
79 reg = <0>;
[all …]
Dimx8mp-verdin.dtsi25 brightness-levels = <0 45 63 88 119 158 203 255>;
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 45 63 88 119 158 203 255>;
44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
51 pinctrl-0 = <&pinctrl_gpio_keys>;
56 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
92 pinctrl-0 = <&pinctrl_reg_eth>;
108 pinctrl-0 = <&pinctrl_usb1_vbus>;
120 pinctrl-0 = <&pinctrl_usb2_vbus>;
[all …]
Dimx8mp-msc-sm2s.dtsi25 pinctrl-0 = <&pinctrl_usb0_vbus>;
36 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
70 lcd0_backlight: backlight-0 {
73 pinctrl-0 = <&pinctrl_lcd0_backlight>;
74 pwms = <&pwm1 0 100000 0>;
75 brightness-levels = <0 255>;
85 pinctrl-0 = <&pinctrl_lcd1_backlight>;
86 pwms = <&pwm2 0 100000 0>;
87 brightness-levels = <0 255>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx53-m53menlo.dts15 pinctrl-0 = <&pinctrl_power_button>;
27 pinctrl-0 = <&pinctrl_power_out>;
35 pinctrl-0 = <&pinctrl_led>;
61 #size-cells = <0>;
63 port@0 {
64 reg = <0>;
83 pinctrl-0 = <&pinctrl_display_gpio>;
85 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
96 pinctrl-0 = <&pinctrl_beeper>;
105 gpio = <&gpio1 2 0>;
[all …]
Dimx53-smd.dts16 reg = <0x70000000 0x40000000>;
24 gpios = <&gpio2 14 0>;
30 gpios = <&gpio2 15 0>;
38 pinctrl-0 = <&pinctrl_esdhc1>;
46 pinctrl-0 = <&pinctrl_esdhc2>;
53 pinctrl-0 = <&pinctrl_uart3>;
60 pinctrl-0 = <&pinctrl_ecspi1>;
64 zigbee: mc1323@0 {
67 reg = <0>;
77 partition@0 {
[all …]
Dimx53-cx9020.dts20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
24 display-0 {
26 #size-cells = <0>;
30 pinctrl-0 = <&pinctrl_ipu_disp0>;
32 port@0 {
33 reg = <0>;
66 #size-cells = <0>;
68 port@0 {
69 reg = <0>;
[all …]
Dimx53-sk-imx53.dts29 reg = <0x70000000 0x20000000>;
53 pinctrl-0 = <&pinctrl_audmux>;
59 pinctrl-0 = <&pinctrl_can1>;
75 pinctrl-0 = <&pinctrl_ecspi1>;
82 pinctrl-0 = <&pinctrl_ecspi2>;
91 pinctrl-0 = <&pinctrl_esdhc1>;
97 pinctrl-0 = <&pinctrl_fec>;
105 #size-cells = <0>;
107 phy0: ethernet-phy@0 {
108 reg = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx53-m53menlo.dts15 pinctrl-0 = <&pinctrl_power_button>;
27 pinctrl-0 = <&pinctrl_power_out>;
35 pinctrl-0 = <&pinctrl_led>;
61 #size-cells = <0>;
63 port@0 {
64 reg = <0>;
83 pinctrl-0 = <&pinctrl_display_gpio>;
85 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
96 pinctrl-0 = <&pinctrl_beeper>;
105 gpio = <&gpio1 2 0>;
[all …]
Dimx53-smd.dts16 reg = <0x70000000 0x40000000>;
24 gpios = <&gpio2 14 0>;
30 gpios = <&gpio2 15 0>;
38 pinctrl-0 = <&pinctrl_esdhc1>;
46 pinctrl-0 = <&pinctrl_esdhc2>;
53 pinctrl-0 = <&pinctrl_uart3>;
60 pinctrl-0 = <&pinctrl_ecspi1>;
64 zigbee: mc1323@0 {
67 reg = <0>;
77 partition@0 {
[all …]
Dimx53-cx9020.dts20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
24 display-0 {
26 #size-cells = <0>;
30 pinctrl-0 = <&pinctrl_ipu_disp0>;
32 port@0 {
33 reg = <0>;
66 #size-cells = <0>;
68 port@0 {
69 reg = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/clk/mediatek/
Dclk-mt7986-topckgen.c176 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
178 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
180 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
182 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
185 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
187 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/coda/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/chips-media/
Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/falcon/
Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), in nvkm_falcon_v1_load_imem()
62 /* code must be padded to 0x40 words */ in nvkm_falcon_v1_load_imem()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/armada/
Darmada_debugfs.c29 return 0; in armada_debugfs_gem_linear_show()
37 for (i = 0x84; i <= 0x1c4; i += 4) { in armada_debugfs_crtc_reg_show()
39 seq_printf(m, "0x%04x: 0x%08x\n", i, v); in armada_debugfs_crtc_reg_show()
42 return 0; in armada_debugfs_crtc_reg_show()
60 if (*off != 0) in armada_debugfs_crtc_reg_write()
61 return 0; in armada_debugfs_crtc_reg_write()
67 if (ret < 0) in armada_debugfs_crtc_reg_write()
69 buf[len] = '\0'; in armada_debugfs_crtc_reg_write()
73 if (reg < 0x84 || reg > 0x1c4 || reg & 3) in armada_debugfs_crtc_reg_write()
101 { "gem_linear", armada_debugfs_gem_linear_show, 0 },
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/armada/
Darmada_debugfs.c29 return 0; in armada_debugfs_gem_linear_show()
37 for (i = 0x84; i <= 0x1c4; i += 4) { in armada_debugfs_crtc_reg_show()
39 seq_printf(m, "0x%04x: 0x%08x\n", i, v); in armada_debugfs_crtc_reg_show()
42 return 0; in armada_debugfs_crtc_reg_show()
60 if (*off != 0) in armada_debugfs_crtc_reg_write()
61 return 0; in armada_debugfs_crtc_reg_write()
67 if (ret < 0) in armada_debugfs_crtc_reg_write()
69 buf[len] = '\0'; in armada_debugfs_crtc_reg_write()
73 if (reg < 0x84 || reg > 0x1c4 || reg & 3) in armada_debugfs_crtc_reg_write()
101 { "gem_linear", armada_debugfs_gem_linear_show, 0 },
[all …]
/kernel/linux/linux-6.6/drivers/soc/tegra/
Dpmc.c63 #define PMC_CNTRL 0x0
74 #define PMC_WAKE_MASK 0x0c
75 #define PMC_WAKE_LEVEL 0x10
76 #define PMC_WAKE_STATUS 0x14
77 #define PMC_SW_WAKE_STATUS 0x18
78 #define PMC_DPD_PADS_ORIDE 0x1c
81 #define DPD_SAMPLE 0x020
82 #define DPD_SAMPLE_ENABLE BIT(0)
83 #define DPD_SAMPLE_DISABLE (0 << 0)
85 #define PWRGATE_TOGGLE 0x30
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/falcon/
Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), in nvkm_falcon_v1_load_imem()
62 /* code must be padded to 0x40 words */ in nvkm_falcon_v1_load_imem()
[all …]
Dgm200.c31 u32 sctl = nvkm_falcon_rd32(falcon, 0x240); in gm200_flcn_tracepc()
32 u32 tidx = nvkm_falcon_rd32(falcon, 0x148); in gm200_flcn_tracepc()
33 int nr = (tidx & 0x00ff0000) >> 16, sp, ip; in gm200_flcn_tracepc()
36 for (sp = 0; sp < nr; sp++) { in gm200_flcn_tracepc()
37 nvkm_falcon_wr32(falcon, 0x148, sp); in gm200_flcn_tracepc()
38 ip = nvkm_falcon_rd32(falcon, 0x14c); in gm200_flcn_tracepc()
47 *(u32 *)img = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8)); in gm200_flcn_pio_dmem_rd()
54 u32 data = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8)); in gm200_flcn_pio_dmem_rd()
57 *(u8 *)img++ = data & 0xff; in gm200_flcn_pio_dmem_rd()
66 nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), BIT(25) | dmem_base); in gm200_flcn_pio_dmem_rd_init()
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcs-ufs-v3.h9 #define QPHY_V3_PCS_UFS_PHY_START 0x000
10 #define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
12 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
13 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
14 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
15 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
16 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
17 #define QPHY_V3_PCS_UFS_READY_STATUS 0x160
18 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
[all …]
Dphy-qcom-qmp-pcs-usb-v6.h10 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
11 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
12 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
13 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
14 #define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
15 #define QPHY_USB_V6_PCS_POWER_STATE_CONFIG1 0x90
16 #define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188
17 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
18 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
19 #define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0
[all …]
Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dregs-gpio-memport-s3c64xx.h14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
Dregs-gpio-memport-s3c64xx.h14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]

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