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/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
Dbnx2x_self_test.c6 #define NA 0xCD
8 #define IDLE_CHK_E1 0x01
9 #define IDLE_CHK_E1H 0x02
10 #define IDLE_CHK_E2 0x04
11 #define IDLE_CHK_E3A0 0x08
12 #define IDLE_CHK_E3B0 0x10
118 /*line 2*/{(0x3), 1, 0x2114,
119 NA, 1, 0, pand_neq,
121 "PCIE: ucorr_err_status is not 0",
122 {NA, NA, 0x0FF010, 0, NA, NA} },
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
Dbnx2x_self_test.c6 #define NA 0xCD
8 #define IDLE_CHK_E1 0x01
9 #define IDLE_CHK_E1H 0x02
10 #define IDLE_CHK_E2 0x04
11 #define IDLE_CHK_E3A0 0x08
12 #define IDLE_CHK_E3B0 0x10
118 /*line 2*/{(0x3), 1, 0x2114,
119 NA, 1, 0, pand_neq,
121 "PCIE: ucorr_err_status is not 0",
122 {NA, NA, 0x0FF010, 0, NA, NA} },
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/verisilicon/
Dhantro_g2_regs.h22 #define G2_REG_VERSION G2_SWREG(0)
28 #define G2_REG_INTERRUPT_DEC_E BIT(0)
30 #define HEVC_DEC_MODE 0xc
31 #define VP9_DEC_MODE 0xd
33 #define BUS_WIDTH_32 0
38 #define g2_strm_swap G2_DEC_REG(2, 28, 0xf)
39 #define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f)
40 #define g2_pic_swap G2_DEC_REG(2, 22, 0x1f)
41 #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf)
42 #define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f)
[all …]
Dhantro_g1_regs.h15 #define G1_REG_INTERRUPT 0x004
26 #define G1_REG_INTERRUPT_DEC_E BIT(0)
27 #define G1_REG_CONFIG 0x008
28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11)
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5)
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0)
46 #define G1_REG_DEC_CTRL0 0x00c
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28)
70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0)
[all …]
Drockchip_vpu2_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/panel/
Dpanel-leadtek-ltk050h3146w.c43 { 0x22, 0x0A }, /* BGR SS GS */
44 { 0x31, 0x00 }, /* column inversion */
45 { 0x53, 0xA2 }, /* VCOM1 */
46 { 0x55, 0xA2 }, /* VCOM2 */
47 { 0x50, 0x81 }, /* VREG1OUT=5V */
48 { 0x51, 0x85 }, /* VREG2OUT=-5V */
49 { 0x62, 0x0D }, /* EQT Time setting */
54 { 0xA0, 0x00 },
55 { 0xA1, 0x1A },
56 { 0xA2, 0x28 },
[all …]
Dpanel-samsung-s6e8aa0.c34 #define PANELCTL_SS_1_800 (0 << 5)
41 #define PANELCTL_CLK1_000 (0 << 3)
43 #define PANELCTL_CLK2_CON_MASK (7 << 0)
44 #define PANELCTL_CLK2_000 (0 << 0)
45 #define PANELCTL_CLK2_001 (1 << 0)
48 #define PANELCTL_INT1_000 (0 << 3)
50 #define PANELCTL_INT2_CON_MASK (7 << 0)
51 #define PANELCTL_INT2_000 (0 << 0)
52 #define PANELCTL_INT2_001 (1 << 0)
55 #define PANELCTL_BICTL_000 (0 << 3)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/panel/
Dpanel-leadtek-ltk050h3146w.c42 { 0x22, 0x0A }, /* BGR SS GS */
43 { 0x31, 0x00 }, /* column inversion */
44 { 0x53, 0xA2 }, /* VCOM1 */
45 { 0x55, 0xA2 }, /* VCOM2 */
46 { 0x50, 0x81 }, /* VREG1OUT=5V */
47 { 0x51, 0x85 }, /* VREG2OUT=-5V */
48 { 0x62, 0x0D }, /* EQT Time setting */
53 { 0xA0, 0x00 },
54 { 0xA1, 0x1A },
55 { 0xA2, 0x28 },
[all …]
Dpanel-samsung-s6e8aa0.c34 #define PANELCTL_SS_1_800 (0 << 5)
41 #define PANELCTL_CLK1_000 (0 << 3)
43 #define PANELCTL_CLK2_CON_MASK (7 << 0)
44 #define PANELCTL_CLK2_000 (0 << 0)
45 #define PANELCTL_CLK2_001 (1 << 0)
48 #define PANELCTL_INT1_000 (0 << 3)
50 #define PANELCTL_INT2_CON_MASK (7 << 0)
51 #define PANELCTL_INT2_000 (0 << 0)
52 #define PANELCTL_INT2_001 (1 << 0)
55 #define PANELCTL_BICTL_000 (0 << 3)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/hantro/
Dhantro_g1_regs.h15 #define G1_REG_INTERRUPT 0x004
26 #define G1_REG_INTERRUPT_DEC_E BIT(0)
27 #define G1_REG_CONFIG 0x008
28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11)
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5)
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0)
46 #define G1_REG_DEC_CTRL0 0x00c
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28)
70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0)
[all …]
Drk3399_vpu_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar9003_aic.c25 0, 3, 9, 15, 21, 27
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
Dar9003_aic.c25 0, 3, 9, 15, 21, 27
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/realtek/
Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/ti-vpe/
Dvpe_regs.h16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/ti/vpe/
Dvpe_regs.h16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
[all …]
/kernel/linux/linux-6.6/sound/soc/amd/include/
Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/kernel/linux/linux-5.10/sound/soc/amd/include/
Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/kernel/linux/linux-5.10/arch/powerpc/math-emu/
Dmath.c80 #define OP31 0x1f /* 31 */
81 #define LFS 0x30 /* 48 */
82 #define LFSU 0x31 /* 49 */
83 #define LFD 0x32 /* 50 */
84 #define LFDU 0x33 /* 51 */
85 #define STFS 0x34 /* 52 */
86 #define STFSU 0x35 /* 53 */
87 #define STFD 0x36 /* 54 */
88 #define STFDU 0x37 /* 55 */
89 #define OP59 0x3b /* 59 */
[all …]
/kernel/linux/linux-6.6/arch/powerpc/math-emu/
Dmath.c29 void *op4) { return 0; }
80 #define OP31 0x1f /* 31 */
81 #define LFS 0x30 /* 48 */
82 #define LFSU 0x31 /* 49 */
83 #define LFD 0x32 /* 50 */
84 #define LFDU 0x33 /* 51 */
85 #define STFS 0x34 /* 52 */
86 #define STFSU 0x35 /* 53 */
87 #define STFD 0x36 /* 54 */
88 #define STFDU 0x37 /* 55 */
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Des8326.c48 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
49 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0);
50 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0);
51 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0);
52 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0);
53 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0);
54 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0);
86 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DAC_VOL, 0, 0xbf, 0, dac_vol_tlv),
88 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
89 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv),
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dvitesse.c15 #define MII_VSC82X4_EXT_PAGE_16E 0x10
16 #define MII_VSC82X4_EXT_PAGE_17E 0x11
17 #define MII_VSC82X4_EXT_PAGE_18E 0x12
20 #define MII_VSC8244_EXT_CON1 0x17
21 #define MII_VSC8244_EXTCON1_INIT 0x0000
22 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
23 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
24 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
25 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
28 #define MII_VSC8244_IMASK 0x19
[all …]

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