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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx53-tx53.dtsi55 reg = <0x70000000 0>;
69 clock-frequency = <0>;
75 #clock-cells = <0>;
82 pinctrl-0 = <&pinctrl_gpio_key>;
95 pinctrl-0 = <&pinctrl_stk5led>;
124 pinctrl-0 = <&pinctrl_can_xcvr>;
134 pinctrl-0 = <&pinctrl_usbh1_vbus>;
145 pinctrl-0 = <&pinctrl_usbotg_vbus>;
167 pinctrl-0 = <&pinctrl_ssi1>;
173 pinctrl-0 = <&pinctrl_can1>;
[all …]
Dimx53-tx53-x03x.dts60 pinctrl-0 = <&pinctrl_rgb24_vga1>;
80 hsync-active = <0>;
81 vsync-active = <0>;
83 pixelclk-active = <0>;
96 hsync-active = <0>;
97 vsync-active = <0>;
99 pixelclk-active = <0>;
112 hsync-active = <0>;
113 vsync-active = <0>;
115 pixelclk-active = <0>;
[all …]
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx53-tx53.dtsi55 reg = <0x70000000 0>;
69 clock-frequency = <0>;
75 #clock-cells = <0>;
82 pinctrl-0 = <&pinctrl_gpio_key>;
95 pinctrl-0 = <&pinctrl_stk5led>;
124 pinctrl-0 = <&pinctrl_can_xcvr>;
134 pinctrl-0 = <&pinctrl_usbh1_vbus>;
145 pinctrl-0 = <&pinctrl_usbotg_vbus>;
167 pinctrl-0 = <&pinctrl_ssi1>;
173 pinctrl-0 = <&pinctrl_can1>;
[all …]
Dimx53-tx53-x03x.dts60 pinctrl-0 = <&pinctrl_rgb24_vga1>;
80 hsync-active = <0>;
81 vsync-active = <0>;
83 pixelclk-active = <0>;
96 hsync-active = <0>;
97 vsync-active = <0>;
99 pixelclk-active = <0>;
112 hsync-active = <0>;
113 vsync-active = <0>;
115 pixelclk-active = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Despi.c56 #define TRICN_CMD_READ 0x11
57 #define TRICN_CMD_WRITE 0x21
71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
95 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init()
96 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init()
97 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init()
100 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init()
102 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init()
104 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init()
105 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb/
Despi.c47 #define TRICN_CMD_READ 0x11
48 #define TRICN_CMD_WRITE 0x21
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
86 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init()
87 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init()
88 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init()
91 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init()
93 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init()
95 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init()
96 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init()
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcs-ufs-v6.h10 #define QPHY_V6_PCS_UFS_PHY_START 0x000
11 #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
16 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
17 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
18 #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
19 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
[all …]
Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Damlogic,meson6-efuse.yaml42 efuse: efuse@0 {
44 reg = <0x0 0x2000>;
51 reg = <0x1b4 0x6>;
55 reg = <0x1f4 0x4>;
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc_hw_sequencer.c33 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
37 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
58 {0, 0, 0},
60 {0x40, 0x40, 0x40},
62 {0x200, 0x40, 0x200},
64 {0x1f4, 0x40, 0x1f4},
66 {0x1a2, 0x20, 0x1a2},
68 {0xff, 0xff, 0},
78 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
80 { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} },
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-pcie-phy.yaml20 const: 0
54 reg = <0x10210000 0x10000>;
55 #phy-cells = <0>;
56 starfive,sys-syscon = <&sys_syscon 0x18>;
57 starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
/kernel/linux/linux-6.6/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/vf/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/kernel/linux/linux-5.10/drivers/clk/meson/
Daxg.h19 #define HHI_MIPI_CNTL0 0x00
20 #define HHI_GP0_PLL_CNTL 0x40
21 #define HHI_GP0_PLL_CNTL2 0x44
22 #define HHI_GP0_PLL_CNTL3 0x48
23 #define HHI_GP0_PLL_CNTL4 0x4c
24 #define HHI_GP0_PLL_CNTL5 0x50
25 #define HHI_GP0_PLL_STS 0x54
26 #define HHI_GP0_PLL_CNTL1 0x58
27 #define HHI_HIFI_PLL_CNTL 0x80
28 #define HHI_HIFI_PLL_CNTL2 0x84
[all …]

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