| /kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| D | dcore0_hmmu0_stlb_masks.h | 24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0
25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0
29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF
32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
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| D | pmmu_hbw_stlb_masks.h | 24 #define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0
25 #define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define PMMU_HBW_STLB_ASID_ASID_SHIFT 0
29 #define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF
32 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/verisilicon/ |
| D | rockchip_vpu981_regs.h | 28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
39 #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1)
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| D | rockchip_vpu2_regs.h | 13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
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| /kernel/linux/linux-6.6/drivers/dma/ti/ |
| D | k3-udma.h | 12 #define UDMA_REV_REG 0x0
13 #define UDMA_PERF_CTL_REG 0x4
14 #define UDMA_EMU_CTL_REG 0x8
15 #define UDMA_PSIL_TO_REG 0x10
16 #define UDMA_UTC_CTL_REG 0x1c
17 #define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
18 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
22 #define UDMA_CHAN_RT_CTL_REG 0x0
23 #define UDMA_CHAN_RT_SWTRIG_REG 0x8
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| /kernel/linux/linux-5.10/drivers/staging/media/hantro/ |
| D | rk3399_vpu_regs.h | 13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/ |
| D | thermal-sensor.yaml | 35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
54 reg = <0 0x0c263000 0 0x1ff>, /* TM */
55 <0 0x0c222000 0 0x1ff>; /* SROT */
65 reg = <0 0x0c265000 0 0x1ff>, /* TM */
66 <0 0x0c223000 0 0x1ff>; /* SROT */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/thermal/ |
| D | thermal-sensor.yaml | 35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
57 reg = <0 0x0c263000 0 0x1ff>, /* TM */
58 <0 0x0c222000 0 0x1ff>; /* SROT */
68 reg = <0 0x0c265000 0 0x1ff>, /* TM */
69 <0 0x0c223000 0 0x1ff>; /* SROT */
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| /kernel/linux/linux-5.10/drivers/dma/ti/ |
| D | k3-udma.h | 12 #define UDMA_REV_REG 0x0
13 #define UDMA_PERF_CTL_REG 0x4
14 #define UDMA_EMU_CTL_REG 0x8
15 #define UDMA_PSIL_TO_REG 0x10
16 #define UDMA_UTC_CTL_REG 0x1c
17 #define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
18 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
22 #define UDMA_CHAN_RT_CTL_REG 0x0
23 #define UDMA_CHAN_RT_SWTRIG_REG 0x8
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| /kernel/linux/linux-6.6/drivers/gpu/host1x/hw/ |
| D | hw_host1x01_sync.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/host1x/hw/ |
| D | hw_host1x01_sync.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
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| /kernel/linux/linux-6.6/drivers/thermal/tegra/ |
| D | tegra210-soctherm.c | 24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
[all …]
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| /kernel/linux/linux-5.10/drivers/thermal/tegra/ |
| D | tegra210-soctherm.c | 24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/media/rkvdec/ |
| D | rkvdec-regs.h | 7 #define RKVDEC_REG_INTERRUPT 0x004
8 #define RKVDEC_INTERRUPT_DEC_E BIT(0)
32 #define RKVDEC_REG_SYSCTRL 0x008
33 #define RKVDEC_IN_ENDIAN BIT(0)
44 #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
45 #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
55 #define RKVDEC_REG_PICPAR 0x00C
56 #define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
58 #define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
59 #define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/media/rkvdec/ |
| D | rkvdec-regs.h | 7 #define RKVDEC_REG_INTERRUPT 0x004
8 #define RKVDEC_INTERRUPT_DEC_E BIT(0)
32 #define RKVDEC_REG_SYSCTRL 0x008
33 #define RKVDEC_IN_ENDIAN BIT(0)
44 #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
45 #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
55 #define RKVDEC_REG_PICPAR 0x00C
56 #define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
58 #define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
59 #define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
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| /kernel/linux/linux-5.10/drivers/net/dsa/ |
| D | bcm_sf2_regs.h | 13 REG_SWITCH_CNTRL = 0,
30 #define MDIO_MASTER_SEL (1 << 0)
33 #define SF2_REV_MASK 0xffff
35 #define SWITCH_TOP_REV_MASK 0xffff
38 #define PHY_REVISION_MASK 0xffff
41 #define IDDQ_BIAS (1 << 0)
48 #define PHY_PHYAD_MASK 0x1F
53 #define RGMII_MODE_EN (1 << 0)
56 #define INT_EPHY (0 << PORT_MODE_SHIFT)
61 #define PORT_MODE_MASK 0x7
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | mc.h | 15 #define MC_INTSTATUS 0x00
16 #define MC_INTMASK 0x04
17 #define MC_ERR_STATUS 0x08
18 #define MC_ERR_ADR 0x0c
19 #define MC_GART_ERROR_REQ 0x30
20 #define MC_EMEM_ADR_CFG 0x54
21 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
22 #define MC_SECURITY_VIOLATION_STATUS 0x74
23 #define MC_EMEM_ARB_CFG 0x90
24 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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| /kernel/linux/linux-6.6/drivers/net/dsa/ |
| D | bcm_sf2_regs.h | 13 REG_SWITCH_CNTRL = 0,
36 #define MDIO_MASTER_SEL (1 << 0)
39 #define SF2_REV_MASK 0xffff
41 #define SWITCH_TOP_REV_MASK 0xffff
44 #define PHY_REVISION_MASK 0xffff
47 #define IDDQ_BIAS (1 << 0)
54 #define PHY_PHYAD_MASK 0x1F
57 #define CROSSBAR_BCM4908_INT_P7 0
59 #define CROSSBAR_BCM4908_EXT_SERDES 0
64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
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| /kernel/linux/linux-6.6/drivers/clk/sifive/ |
| D | sifive-prci.h | 28 #define PRCI_COREPLLCFG0_OFFSET 0x4
29 #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
30 #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
32 #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
34 #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
36 #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
38 #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
40 #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
42 #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
45 #define PRCI_COREPLLCFG1_OFFSET 0x8
[all …]
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ingenic/ |
| D | jz4740_ecc.c | 19 #define JZ_REG_NAND_ECC_CTRL 0x00
20 #define JZ_REG_NAND_DATA 0x04
21 #define JZ_REG_NAND_PAR0 0x08
22 #define JZ_REG_NAND_PAR1 0x0C
23 #define JZ_REG_NAND_PAR2 0x10
24 #define JZ_REG_NAND_IRQ_STAT 0x14
25 #define JZ_REG_NAND_IRQ_CTRL 0x18
26 #define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2))
32 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
39 #define JZ_NAND_STATUS_ERROR BIT(0)
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ingenic/ |
| D | jz4740_ecc.c | 19 #define JZ_REG_NAND_ECC_CTRL 0x00
20 #define JZ_REG_NAND_DATA 0x04
21 #define JZ_REG_NAND_PAR0 0x08
22 #define JZ_REG_NAND_PAR1 0x0C
23 #define JZ_REG_NAND_PAR2 0x10
24 #define JZ_REG_NAND_IRQ_STAT 0x14
25 #define JZ_REG_NAND_IRQ_CTRL 0x18
26 #define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2))
32 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
39 #define JZ_NAND_STATUS_ERROR BIT(0)
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| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | au1200fb.h | 33 #define AU1200_LCD_ADDR 0xB5000000
64 uint32 reserved2[(0x0100-0x0058)/4];
77 uint32 reserved3[(0x0400-0x0180)/4];
79 volatile uint32 palette[(0x0800-0x0400)/4];
86 #define LCD_SCREEN_SX (0x07FF<<19)
87 #define LCD_SCREEN_SY (0x07FF<< 8)
90 #define LCD_SCREEN_PT (7<<0)
91 #define LCD_SCREEN_PT_TFT (0<<0)
94 #define LCD_SCREEN_PT_CSTN (1<<0)
95 #define LCD_SCREEN_PT_CDSTN (2<<0)
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | au1200fb.h | 33 #define AU1200_LCD_ADDR 0xB5000000
64 uint32 reserved2[(0x0100-0x0058)/4];
77 uint32 reserved3[(0x0400-0x0180)/4];
79 volatile uint32 palette[(0x0800-0x0400)/4];
86 #define LCD_SCREEN_SX (0x07FF<<19)
87 #define LCD_SCREEN_SY (0x07FF<< 8)
90 #define LCD_SCREEN_PT (7<<0)
91 #define LCD_SCREEN_PT_TFT (0<<0)
94 #define LCD_SCREEN_PT_CSTN (1<<0)
95 #define LCD_SCREEN_PT_CDSTN (2<<0)
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| /kernel/linux/linux-6.6/drivers/gpu/ipu-v3/ |
| D | ipu-ic.c | 18 #define IC_CONF 0x0000
19 #define IC_PRP_ENC_RSC 0x0004
20 #define IC_PRP_VF_RSC 0x0008
21 #define IC_PP_RSC 0x000C
22 #define IC_CMBP_1 0x0010
23 #define IC_CMBP_2 0x0014
24 #define IC_IDMAC_1 0x0018
25 #define IC_IDMAC_2 0x001C
26 #define IC_IDMAC_3 0x0020
27 #define IC_IDMAC_4 0x0024
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| /kernel/linux/linux-5.10/drivers/gpu/ipu-v3/ |
| D | ipu-ic.c | 18 #define IC_CONF 0x0000
19 #define IC_PRP_ENC_RSC 0x0004
20 #define IC_PRP_VF_RSC 0x0008
21 #define IC_PP_RSC 0x000C
22 #define IC_CMBP_1 0x0010
23 #define IC_CMBP_2 0x0014
24 #define IC_IDMAC_1 0x0018
25 #define IC_IDMAC_2 0x001C
26 #define IC_IDMAC_3 0x0020
27 #define IC_IDMAC_4 0x0024
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