Home
last modified time | relevance | path

Searched +full:0 +full:x22c (Results 1 – 25 of 225) sorted by relevance

123456789

/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra30.c36 .id = 0x00,
40 .id = 0x01,
44 .reg = 0x228,
48 .reg = 0x2e8,
49 .shift = 0,
50 .mask = 0xff,
51 .def = 0x4e,
54 .id = 0x02,
58 .reg = 0x228,
62 .reg = 0x2f4,
[all …]
Dtegra114.c15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0x4e,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
Dtegra124.c15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
26 .mask = 0xff,
27 .def = 0xc2,
30 .id = 0x02,
34 .reg = 0x228,
38 .reg = 0x2f4,
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
Dtegra114.c15 .id = 0x00,
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
27 .id = 0x01,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
38 .mask = 0xff,
[all …]
Dtegra30.c37 .id = 0x00,
42 .reg = 0x34c,
43 .shift = 0,
44 .mask = 0xff,
45 .def = 0x0,
50 .id = 0x01,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
61 .mask = 0xff,
[all …]
Dtegra124.c16 .id = 0x00,
21 .reg = 0x34c,
22 .shift = 0,
23 .mask = 0xff,
24 .def = 0x0,
28 .id = 0x01,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
39 .mask = 0xff,
[all …]
Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
32 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
Dccu-sun20i-d1-r.c26 r_ahb_apb0_parents, 0x000,
27 0, 5, /* M */
30 0);
34 r_ahb_apb0_parents, 0x00c,
35 0, 5, /* M */
38 0);
42 0x11c, BIT(0), 0);
44 0x12c, BIT(0), 0);
46 0x1ac, BIT(0), 0);
53 r_ir_rx_parents, 0x1c0,
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-footbridge/
Dnetwinder-hw.c28 #define IRDA_IO_BASE 0x180
29 #define GP1_IO_BASE 0x338
30 #define GP2_IO_BASE 0x33a
37 outb(0x87, 0x370); in wb977_open()
38 outb(0x87, 0x370); in wb977_open()
43 outb(0xaa, 0x370); in wb977_close()
48 outb(reg, 0x370); in wb977_wb()
49 outb(val, 0x371); in wb977_wb()
54 outb(reg, 0x370); in wb977_ww()
55 outb(val >> 8, 0x371); in wb977_ww()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-footbridge/
Dnetwinder-hw.c28 #define IRDA_IO_BASE 0x180
29 #define GP1_IO_BASE 0x338
30 #define GP2_IO_BASE 0x33a
37 outb(0x87, 0x370); in wb977_open()
38 outb(0x87, 0x370); in wb977_open()
43 outb(0xaa, 0x370); in wb977_close()
48 outb(reg, 0x370); in wb977_wb()
49 outb(val, 0x371); in wb977_wb()
54 outb(reg, 0x370); in wb977_ww()
55 outb(val >> 8, 0x371); in wb977_ww()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml28 "^.*@[0-9a-f]+$":
51 reg = <0x1fff7800 0x400>;
56 reg = <0x22c 0x2>;
60 reg = <0xe4 0x8>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml32 "^.*@[0-9a-f]+$":
55 reg = <0x1fff7800 0x400>;
60 reg = <0x22c 0x2>;
64 reg = <0xe4 0x8>;
/kernel/linux/linux-6.6/drivers/net/ethernet/sunplus/
Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/kernel/linux/linux-5.10/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/kernel/linux/linux-6.6/include/linux/bcma/
Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
/kernel/linux/linux-6.6/sound/soc/fsl/
Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
/kernel/linux/linux-6.6/drivers/devfreq/event/
Dexynos-ppmu.h13 PPMU_DISABLE = 0,
18 PPMU_PMNCNT0 = 0,
30 PPMU_RO_BUSY_CYCLE_CNT = 0x0,
31 PPMU_WO_BUSY_CYCLE_CNT = 0x1,
32 PPMU_RW_BUSY_CYCLE_CNT = 0x2,
33 PPMU_RO_REQUEST_CNT = 0x3,
34 PPMU_WO_REQUEST_CNT = 0x4,
35 PPMU_RO_DATA_CNT = 0x5,
36 PPMU_WO_DATA_CNT = 0x6,
37 PPMU_RO_LATENCY = 0x12,
[all …]
/kernel/linux/linux-5.10/drivers/devfreq/event/
Dexynos-ppmu.h13 PPMU_DISABLE = 0,
18 PPMU_PMNCNT0 = 0,
30 PPMU_RO_BUSY_CYCLE_CNT = 0x0,
31 PPMU_WO_BUSY_CYCLE_CNT = 0x1,
32 PPMU_RW_BUSY_CYCLE_CNT = 0x2,
33 PPMU_RO_REQUEST_CNT = 0x3,
34 PPMU_WO_REQUEST_CNT = 0x4,
35 PPMU_RO_DATA_CNT = 0x5,
36 PPMU_WO_DATA_CNT = 0x6,
37 PPMU_RO_LATENCY = 0x12,
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]

123456789