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/kernel/linux/linux-6.6/arch/arc/include/asm/
Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
[all …]
/kernel/linux/linux-5.10/drivers/pcmcia/
Dpxa2xx_cm_x255.c29 gpio_direction_output(GPIO_PCMCIA_RESET, 0); in cmx255_pcmcia_hw_init()
31 if (skt->nr == 0) { in cmx255_pcmcia_hw_init()
43 return 0; in cmx255_pcmcia_hw_init()
55 state->vs_3v = 0; in cmx255_pcmcia_socket_state()
56 state->vs_Xv = 0; in cmx255_pcmcia_socket_state()
64 case 0: in cmx255_pcmcia_configure_socket()
66 gpio_set_value(GPIO_PCMCIA_SKTSEL, 0); in cmx255_pcmcia_configure_socket()
70 gpio_set_value(GPIO_PCMCIA_RESET, 0); in cmx255_pcmcia_configure_socket()
79 gpio_set_value(GPIO_PCMCIA_RESET, 0); in cmx255_pcmcia_configure_socket()
84 return 0; in cmx255_pcmcia_configure_socket()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Drenesas,rz-ssi.yaml65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
75 bit[11] - LVL = 0, Detects based on the edge
77 bit[15] - TM = 0, Single transfer mode
[all …]
/kernel/linux/linux-5.10/arch/arc/include/asm/
Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h11 BaseBand_Config_PHY_REG = 0,
15 #define RTL8187_REQT_READ 0xc0
16 #define RTL8187_REQT_WRITE 0x40
17 #define RTL8187_REQ_GET_REGS 0x05
18 #define RTL8187_REQ_SET_REGS 0x05
24 #define BB_ANTATTEN_CHAN14 0x0c
25 #define BB_ANTENNA_B 0x40
33 #define RTL8190_EEPROM_ID 0x8129
34 #define EEPROM_VID 0x02
35 #define EEPROM_DID 0x04
[all …]
/kernel/linux/linux-5.10/drivers/usb/serial/
Dsafe_serial.c35 * 0..N-2 data and optional padding
38 * bits 1-0 top two bits of 10 bit CRC
43 * + 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 | 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 +
85 module_param(safe, bool, 0);
88 module_param(padded, bool, 0);
91 #define CDC_DEVICE_CLASS 0x02
93 #define CDC_INTERFACE_CLASS 0x02
94 #define CDC_INTERFACE_SUBCLASS 0x06
96 #define LINEO_INTERFACE_CLASS 0xff
98 #define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01
[all …]
/kernel/linux/linux-6.6/drivers/usb/serial/
Dsafe_serial.c35 * 0..N-2 data and optional padding
38 * bits 1-0 top two bits of 10 bit CRC
43 * + 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 | 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 +
85 module_param(safe, bool, 0);
88 module_param(padded, bool, 0);
91 #define CDC_DEVICE_CLASS 0x02
93 #define CDC_INTERFACE_CLASS 0x02
94 #define CDC_INTERFACE_SUBCLASS 0x06
96 #define LINEO_INTERFACE_CLASS 0xff
98 #define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dintel_msic.h13 #define INTEL_MSIC_ID0 0x000 /* RO */
14 #define INTEL_MSIC_ID1 0x001 /* RO */
17 #define INTEL_MSIC_IRQLVL1 0x002
18 #define INTEL_MSIC_ADC1INT 0x003
19 #define INTEL_MSIC_CCINT 0x004
20 #define INTEL_MSIC_PWRSRCINT 0x005
21 #define INTEL_MSIC_PWRSRCINT1 0x006
22 #define INTEL_MSIC_CHRINT 0x007
23 #define INTEL_MSIC_CHRINT1 0x008
24 #define INTEL_MSIC_RTCIRQ 0x009
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
Dhw.h32 (0xffffffff >> (31 - ((1 ? field) - (0 ? field)))) << (0 ? field))
35 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
137 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
143 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
144 * 0x02 dcb entry's "or" value (or 00 for inactive)
145 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
146 * 0x08 or 0x09 pxclk in MHz
147 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
198 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); in NVSetEnablePalette()
205 return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); in NVGetEnablePalette()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
Dhw.h32 (0xffffffff >> (31 - ((1 ? field) - (0 ? field)))) << (0 ? field))
35 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
137 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
143 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
144 * 0x02 dcb entry's "or" value (or 00 for inactive)
145 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
146 * 0x08 or 0x09 pxclk in MHz
147 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
198 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); in NVSetEnablePalette()
205 return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); in NVGetEnablePalette()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/sis/
Dinitdef.h77 #define VB_SIS301 0x0001
78 #define VB_SIS301B 0x0002
79 #define VB_SIS302B 0x0004
80 #define VB_SIS301LV 0x0008
81 #define VB_SIS302LV 0x0010
82 #define VB_SIS302ELV 0x0020
83 #define VB_SIS301C 0x0040
84 #define VB_SIS307T 0x0080
85 #define VB_SIS307LV 0x0100
86 #define VB_UMC 0x4000
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/sis/
Dinitdef.h77 #define VB_SIS301 0x0001
78 #define VB_SIS301B 0x0002
79 #define VB_SIS302B 0x0004
80 #define VB_SIS301LV 0x0008
81 #define VB_SIS302LV 0x0010
82 #define VB_SIS302ELV 0x0020
83 #define VB_SIS301C 0x0040
84 #define VB_SIS307T 0x0080
85 #define VB_SIS307LV 0x0100
86 #define VB_UMC 0x4000
[all …]
/kernel/linux/linux-5.10/drivers/hwmon/
Dasb100.c23 * asb100 7 3 1 4 0x31 0x0694 yes no
41 static const unsigned short normal_i2c[] = { 0x2d, I2C_CLIENT_END };
44 module_param_array(force_subclients, short, NULL, 0);
48 /* Voltage IN registers 0-6 */
49 #define ASB100_REG_IN(nr) (0x20 + (nr))
50 #define ASB100_REG_IN_MAX(nr) (0x2b + (nr * 2))
51 #define ASB100_REG_IN_MIN(nr) (0x2c + (nr * 2))
54 #define ASB100_REG_FAN(nr) (0x28 + (nr))
55 #define ASB100_REG_FAN_MIN(nr) (0x3b + (nr))
58 static const u16 asb100_reg_temp[] = {0, 0x27, 0x150, 0x250, 0x17};
[all …]
/kernel/linux/linux-6.6/drivers/hwmon/
Dasb100.c23 * asb100 7 3 1 4 0x31 0x0694 yes no
41 static const unsigned short normal_i2c[] = { 0x2d, I2C_CLIENT_END };
44 module_param_array(force_subclients, short, NULL, 0);
48 /* Voltage IN registers 0-6 */
49 #define ASB100_REG_IN(nr) (0x20 + (nr))
50 #define ASB100_REG_IN_MAX(nr) (0x2b + (nr * 2))
51 #define ASB100_REG_IN_MIN(nr) (0x2c + (nr * 2))
54 #define ASB100_REG_FAN(nr) (0x28 + (nr))
55 #define ASB100_REG_FAN_MIN(nr) (0x3b + (nr))
58 static const u16 asb100_reg_temp[] = {0, 0x27, 0x150, 0x250, 0x17};
[all …]
/kernel/linux/linux-5.10/sound/drivers/opl4/
Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/kernel/linux/linux-6.6/sound/drivers/opl4/
Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/b43/
Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
/kernel/linux/linux-6.6/include/drm/display/
Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
[all …]

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