| /kernel/linux/linux-6.6/arch/arm/mach-s3c/ |
| D | map-s3c64xx.h | 22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | map-s3c64xx.h | 22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
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| D | map-s3c24xx.h | 19 #define S3C2410_PA_IRQ (0x4A000000)
23 #define S3C2410_PA_MEMCTRL (0x48000000)
27 #define S3C2410_PA_TIMER (0x51000000)
34 #define S3C2410_PA_USBDEV (0x52000000)
38 #define S3C2410_PA_WATCHDOG (0x53000000)
52 #define S3C2410_PA_USBHOST (0x49000000)
55 #define S3C2416_PA_HSUDC (0x49800000)
59 #define S3C2410_PA_DMA (0x4B000000)
63 #define S3C2410_PA_CLKPWR (0x4C000000)
66 #define S3C2410_PA_LCD (0x4D000000)
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/airoha/ |
| D | en7523.dtsi | 20 reg = <0x84000000 0xA00000>;
25 reg = <0x84B00000 0x100000>;
30 reg = <0x85000000 0x1A00000>;
35 reg = <0x86B00000 0x100000>;
40 reg = <0x86D00000 0x100000>;
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x1>;
91 reg = <0x1fa20000 0x400>,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qcom,lcc.txt | 19 reg = <0x28000000 0x1000>;
|
| /kernel/linux/linux-5.10/arch/sh/boards/mach-rsk/ |
| D | devices-rsk7264.c | 24 [0] = {
25 .start = 0x28000000,
26 .end = 0x280000ff,
|
| /kernel/linux/linux-6.6/arch/sh/boards/mach-rsk/ |
| D | devices-rsk7264.c | 24 [0] = {
25 .start = 0x28000000,
26 .end = 0x280000ff,
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | toshiba,visconti-dwmac.yaml | 64 reg = <0 0x28000000 0 0x10000>;
76 #address-cells = <0x1>;
77 #size-cells = <0x0>;
82 reg = <0x1>;
|
| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | fbio.h | 10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | fbio.h | 10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | qcom,lcc.yaml | 117 reg = <0x28000000 0x1000>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-stm.yaml | 90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
|
| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| D | palmtx.h | 71 #define PALMTX_PCMCIA_PHYS 0x28000000
72 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
73 #define PALMTX_PCMCIA_SIZE 0x100000
75 #define PALMTX_PHYS_RAM_START 0xa0000000
76 #define PALMTX_PHYS_IO_START 0x40000000
78 #define PALMTX_STR_BASE 0xa0200000
80 #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
85 #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
86 #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
95 #define PALMTX_BAT_MAX_CURRENT 0 /* unknown */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv40.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp()
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
49 nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv40.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp()
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
36 !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
49 nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
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| /kernel/linux/linux-5.10/arch/arm/configs/ |
| D | lpc18xx_defconfig | 23 CONFIG_DRAM_BASE=0x28000000
24 CONFIG_DRAM_SIZE=0x02000000
25 CONFIG_FLASH_MEM_BASE=0x1b000000
26 CONFIG_FLASH_SIZE=0x00080000
27 CONFIG_ZBOOT_ROM_TEXT=0x0
28 CONFIG_ZBOOT_ROM_BSS=0x0
|
| /kernel/linux/linux-6.6/arch/arm/configs/ |
| D | lpc18xx_defconfig | 21 CONFIG_DRAM_BASE=0x28000000
22 CONFIG_DRAM_SIZE=0x02000000
23 CONFIG_FLASH_MEM_BASE=0x1b000000
24 CONFIG_FLASH_SIZE=0x00080000
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie.txt | 32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
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| D | brcm,iproc-pcie.yaml | 117 reg = <0x18012000 0x1000>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
123 linux,pci-domain = <0>;
125 bus-range = <0x00 0xff>;
130 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
131 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
133 phys = <&phy 0 5>;
137 brcm,pcie-ob-axi-offset = <0x00000000>;
155 reg = <0x18013000 0x1000>;
[all …]
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| D | nvidia,tegra20-pcie.txt | 27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/lpc/ |
| D | lpc4337-ciaa.dts | 35 reg = <0x28000000 0x0800000>; /* 8 MB */
173 pinctrl-0 = <&i2c0_pins>;
178 reg = <0x50>;
183 reg = <0x51>;
188 reg = <0x54>;
196 pinctrl-0 = <&enet_rmii_pins>;
206 pinctrl-0 = <&ssp_pins>;
214 pinctrl-0 = <&uart2_pins>;
220 pinctrl-0 = <&uart3_pins>;
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | lpc4337-ciaa.dts | 35 reg = <0x28000000 0x0800000>; /* 8 MB */
173 pinctrl-0 = <&i2c0_pins>;
178 reg = <0x50>;
183 reg = <0x51>;
188 reg = <0x54>;
196 pinctrl-0 = <&enet_rmii_pins>;
206 pinctrl-0 = <&ssp_pins>;
214 pinctrl-0 = <&uart2_pins>;
220 pinctrl-0 = <&uart3_pins>;
|
| /kernel/linux/linux-6.6/drivers/soc/tegra/cbb/ |
| D | tegra194-cbb.c | 27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8ulp-evk.dts | 20 reg = <0x0 0x80000000 0 0x80000000>;
31 size = <0 0x28000000>;
36 reg = <0 0xa8600000 0 0x1000000>;
41 reg = <0 0x1fff8000 0 0x1000>;
46 reg = <0 0xaff00000 0 0x8000>;
51 reg = <0 0xaff08000 0 0x8000>;
56 reg = <0 0xaff10000 0 0x8000>;
61 reg = <0 0xaff18000 0 0x8000>;
67 reg = <0 0xa8400000 0 0x100000>;
76 #clock-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.txt | 77 reg = <0x18012000 0x1000>;
80 interrupt-map-mask = <0 0 0 0>;
81 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
83 linux,pci-domain = <0>;
85 bus-range = <0x00 0xff>;
90 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
91 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
93 phys = <&phy 0 5>;
97 brcm,pcie-ob-axi-offset = <0x00000000>;
115 reg = <0x18013000 0x1000>;
[all …]
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