0x290 (full) in projects: kernel - OpenGrok search results

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Searched +full:0 +full:x290 (Results 1 – 25 of 213) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
D	dpu_9_0_sm8550.h	12 .max_mixer_blendstages = 0xb, 24 .base = 0, .len = 0x494, 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, [all …]
/kernel/linux/linux-5.10/Documentation/hwmon/
D	lm78.rst	`10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports) 20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports) 64 inputs can measure voltages between 0 and 4.08 volts, with a resolution`
/kernel/linux/linux-6.6/Documentation/hwmon/
D	lm78.rst	`10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports) 20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports) 64 inputs can measure voltages between 0 and 4.08 volts, with a resolution`
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
D	amlogic,a1-spifc.yaml	`37 reg = <0xfd000400 0x290>; 40 #size-cells = <0>;`
/kernel/linux/linux-6.6/drivers/clk/mediatek/
D	clk-mt6795-apmixedsys.c	`15 #define REG_REF2USB 0x8 16 #define REG_AP_PLL_CON7 0x1c 17 #define MD1_MTCMOS_OFF BIT(0) 23 #define MT6795_CON0_EN BIT(0) 43 .pll_en_bit = 0, \ 47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO, 48 21, 0x204, 24, 0x0, 0x204, 0), 49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 50 21, 0x220, 4, 0x0, 0x224, 0), 51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR, [all …]`
D	clk-mt8173-apmixedsys.c	17 #define REGOFF_REF2USB 0x8 18 #define REGOFF_HDMI_REF 0x40 52 { .div = 0, .freq = MT8173_PLL_FMAX }, 61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, 62 21, 0x204, 24, 0x0, 0x204, 0), 63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, 64 21, 0x214, 24, 0x0, 0x214, 0), 65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 66 0x220, 4, 0x0, 0x224, 0), 67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, [all …]
D	clk-mt8135-apmixedsys.c	38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0), 39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), 40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2… 41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23… 42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, … 43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0), 44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0), 45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), 46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), 47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), [all …]
/kernel/linux/linux-5.10/arch/x86/include/uapi/asm/
D	bootparam.h	`6 #define SETUP_NONE 0 20 #define RAMDISK_IMAGE_START_MASK 0x07FF 21 #define RAMDISK_PROMPT_FLAG 0x8000 22 #define RAMDISK_LOAD_FLAG 0x4000 25 #define LOADED_HIGH (1<<0) 32 #define XLF_KERNEL_64 (1<<0) 54 __u8 data[0]; 176 struct screen_info screen_info; /* 0x000 / 177 struct apm_bios_info apm_bios_info; / 0x040 / 178 __u8 _pad2[4]; / 0x054 */ [all …]`
/kernel/linux/linux-6.6/arch/x86/include/uapi/asm/
D	bootparam.h	`6 #define SETUP_NONE 0 22 #define RAMDISK_IMAGE_START_MASK 0x07FF 23 #define RAMDISK_PROMPT_FLAG 0x8000 24 #define RAMDISK_LOAD_FLAG 0x4000 27 #define LOADED_HIGH (1<<0) 34 #define XLF_KERNEL_64 (1<<0) 187 struct screen_info screen_info; /* 0x000 / 188 struct apm_bios_info apm_bios_info; / 0x040 / 189 __u8 _pad2[4]; / 0x054 / 190 __u64 tboot_addr; / 0x058 */ [all …]`
/kernel/linux/linux-6.6/drivers/clk/meson/
D	axg.h	`19 #define HHI_GP0_PLL_CNTL 0x40 20 #define HHI_GP0_PLL_CNTL2 0x44 21 #define HHI_GP0_PLL_CNTL3 0x48 22 #define HHI_GP0_PLL_CNTL4 0x4c 23 #define HHI_GP0_PLL_CNTL5 0x50 24 #define HHI_GP0_PLL_STS 0x54 25 #define HHI_GP0_PLL_CNTL1 0x58 26 #define HHI_HIFI_PLL_CNTL 0x80 27 #define HHI_HIFI_PLL_CNTL2 0x84 28 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]`
D	g12a.h	`20 #define HHI_MIPI_CNTL0 0x000 21 #define HHI_MIPI_CNTL1 0x004 22 #define HHI_MIPI_CNTL2 0x008 23 #define HHI_MIPI_STS 0x00C 24 #define HHI_GP0_PLL_CNTL0 0x040 25 #define HHI_GP0_PLL_CNTL1 0x044 26 #define HHI_GP0_PLL_CNTL2 0x048 27 #define HHI_GP0_PLL_CNTL3 0x04C 28 #define HHI_GP0_PLL_CNTL4 0x050 29 #define HHI_GP0_PLL_CNTL5 0x054 [all …]`
D	meson8b.h	16 * Register offsets from the HardKernel[0] data sheet are listed in comment 20 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 22 #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet / 23 #define HHI_GP_PLL_CNTL2 0x44 / 0x11 offset in data sheet / 24 #define HHI_GP_PLL_CNTL3 0x48 / 0x12 offset in data sheet / 25 #define HHI_GP_PLL_CNTL4 0x4C / 0x13 offset in data sheet / 26 #define HHI_GP_PLL_CNTL5 0x50 / 0x14 offset in data sheet / 27 #define HHI_VIID_CLK_DIV 0x128 / 0x4a offset in data sheet / 28 #define HHI_VIID_CLK_CNTL 0x12c / 0x4b offset in data sheet / 29 #define HHI_GCLK_MPEG0 0x140 / 0x50 offset in data sheet */ [all …]
/kernel/linux/linux-6.6/sound/soc/tegra/
D	tegra210_mixer.h	`13 #define TEGRA210_MIXER_RX1_SOFT_RESET 0x04 14 #define TEGRA210_MIXER_RX1_STATUS 0x10 15 #define TEGRA210_MIXER_RX1_CIF_CTRL 0x24 16 #define TEGRA210_MIXER_RX1_CTRL 0x28 17 #define TEGRA210_MIXER_RX1_PEAK_CTRL 0x2c 18 #define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30 21 #define TEGRA210_MIXER_TX1_ENABLE 0x280 22 #define TEGRA210_MIXER_TX1_SOFT_RESET 0x284 23 #define TEGRA210_MIXER_TX1_STATUS 0x290 24 #define TEGRA210_MIXER_TX1_INT_STATUS 0x294 [all …]`
/kernel/linux/linux-5.10/drivers/clk/meson/
D	axg.h	`19 #define HHI_MIPI_CNTL0 0x00 20 #define HHI_GP0_PLL_CNTL 0x40 21 #define HHI_GP0_PLL_CNTL2 0x44 22 #define HHI_GP0_PLL_CNTL3 0x48 23 #define HHI_GP0_PLL_CNTL4 0x4c 24 #define HHI_GP0_PLL_CNTL5 0x50 25 #define HHI_GP0_PLL_STS 0x54 26 #define HHI_GP0_PLL_CNTL1 0x58 27 #define HHI_HIFI_PLL_CNTL 0x80 28 #define HHI_HIFI_PLL_CNTL2 0x84 [all …]`
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
D	edd.h	`9 #define EDDNR 0x1e9 10 #define EDDBUF 0xd00 14 #define CHECKEXTENSIONSPRESENT 0x41 15 #define GETDEVICEPARAMETERS 0x48 16 #define LEGACYGETDEVICEPARAMETERS 0x08 17 #define EDDMAGIC1 0x55AA 18 #define EDDMAGIC2 0xAA55 19 #define READ_SECTORS 0x02 20 #define EDD_MBR_SIG_OFFSET 0x1B8 21 #define EDD_MBR_SIG_BUF 0x290 [all …]`
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
D	imxrt1050-pinfunc.h	10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
D	imx8mq-pinfunc.h	15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
D	imx8mm-pinfunc.h	14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
D	imx8mq-pinfunc.h	15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
D	imx8mm-pinfunc.h	14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
D	nwl-dsi.h	`12 #define NWL_DSI_CFG_NUM_LANES 0x0 13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4 14 #define NWL_DSI_CFG_T_PRE 0x8 15 #define NWL_DSI_CFG_T_POST 0xc 16 #define NWL_DSI_CFG_TX_GAP 0x10 17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14 18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c 20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20 21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24 [all …]`
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
D	nwl-dsi.h	`12 #define NWL_DSI_CFG_NUM_LANES 0x0 13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4 14 #define NWL_DSI_CFG_T_PRE 0x8 15 #define NWL_DSI_CFG_T_POST 0xc 16 #define NWL_DSI_CFG_TX_GAP 0x10 17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14 18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c 20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20 21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24 [all …]`
/kernel/linux/linux-5.10/arch/sh/include/mach-sdk7786/mach/
D	fpga.h	`9 #define SRSTR 0x000 10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */ 12 #define INTASR 0x010 13 #define INTAMR 0x020 14 #define MODSWR 0x030 15 #define INTTESTR 0x040 16 #define SYSSR 0x050 17 #define NRGPR 0x060 19 #define NMISR 0x070 20 #define NMISR_MAN_NMI BIT(0) [all …]`
/kernel/linux/linux-6.6/arch/sh/include/mach-sdk7786/mach/
D	fpga.h	`9 #define SRSTR 0x000 10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */ 12 #define INTASR 0x010 13 #define INTAMR 0x020 14 #define MODSWR 0x030 15 #define INTTESTR 0x040 16 #define SYSSR 0x050 17 #define NRGPR 0x060 19 #define NMISR 0x070 20 #define NMISR_MAN_NMI BIT(0) [all …]`
/kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/
D	rk3066_hdmi.h	`10 #define GRF_SOC_CON0 0x150 13 #define DDC_SEGMENT_ADDR 0x30 15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11 17 #define N_32K 0x1000 18 #define N_441K 0x1880 19 #define N_882K 0x3100 20 #define N_1764K 0x6200 21 #define N_48K 0x1800 22 #define N_96K 0x3000 23 #define N_192K 0x6000 [all …]`

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