| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra30-cpu-opp.dtsi | 10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
52 opp-supported-hw = <0x1F 0x0C01>;
58 opp-supported-hw = <0x1F 0x0200>;
64 opp-supported-hw = <0x1F 0x0C00>;
[all …]
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| D | imx23-pinfunc.h | 19 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
20 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
21 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
22 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
23 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
24 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
25 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
26 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
27 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
28 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
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| D | imx28-pinfunc.h | 19 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
20 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
21 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
22 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
23 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
24 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
25 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
26 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
27 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
28 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
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| D | armada-375.dtsi | 36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/ |
| D | tegra30-cpu-opp.dtsi | 10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | marvell-pp2.txt | 48 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
58 reg = <0xf0000 0xa000>,
59 <0xc0000 0x3060>,
60 <0xc4000 0x100>,
61 <0xc5000 0x100>;
67 port-id = <0>;
82 cpm_ethernet: ethernet@0 {
84 reg = <0x0 0x100000>, <0x129000 0xb000>;
102 port-id = <0>;
103 gop-port-id = <0>;
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | rs780d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | rs780d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
[all …]
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| /kernel/linux/linux-5.10/drivers/crypto/qce/ |
| D | regs-v5.h | 11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
[all …]
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| /kernel/linux/linux-6.6/drivers/crypto/qce/ |
| D | regs-v5.h | 11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/mxs/ |
| D | imx23-pinfunc.h | 13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
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| D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | marvell,pp2.yaml | 32 const: 0
59 '^(ethernet-)?port@[0-2]$':
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
165 '^(ethernet-)?port@[0-2]$':
187 '^(ethernet-)?port@[0-1]$':
204 #size-cells = <0>;
206 reg = <0xf0000 0xa000>,
207 <0xc0000 0x3060>,
208 <0xc4000 0x100>,
209 <0xc5000 0x100>;
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/ |
| D | rt2800pci.c | 60 for (i = 0; i < 200; i++) { in rt2800pci_mcu_status()
75 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); in rt2800pci_mcu_status()
76 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); in rt2800pci_mcu_status()
97 u32 reg = 0; in rt2800pci_eepromregister_write()
121 case 0: in rt2800pci_read_eeprom_pci()
131 eeprom.reg_data_in = 0; in rt2800pci_read_eeprom_pci()
132 eeprom.reg_data_out = 0; in rt2800pci_read_eeprom_pci()
133 eeprom.reg_data_clock = 0; in rt2800pci_read_eeprom_pci()
134 eeprom.reg_chip_select = 0; in rt2800pci_read_eeprom_pci()
139 return 0; in rt2800pci_read_eeprom_pci()
[all …]
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| D | rt73usb.h | 20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/ralink/rt2x00/ |
| D | rt2800pci.c | 60 for (i = 0; i < 200; i++) { in rt2800pci_mcu_status()
75 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); in rt2800pci_mcu_status()
76 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); in rt2800pci_mcu_status()
97 u32 reg = 0; in rt2800pci_eepromregister_write()
121 case 0: in rt2800pci_read_eeprom_pci()
131 eeprom.reg_data_in = 0; in rt2800pci_read_eeprom_pci()
132 eeprom.reg_data_out = 0; in rt2800pci_read_eeprom_pci()
133 eeprom.reg_data_clock = 0; in rt2800pci_read_eeprom_pci()
134 eeprom.reg_chip_select = 0; in rt2800pci_read_eeprom_pci()
139 return 0; in rt2800pci_read_eeprom_pci()
[all …]
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| D | rt73usb.h | 20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/ |
| D | armada-375.dtsi | 36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-altera.c | 24 #define RP_TX_REG0 0x2000
25 #define RP_TX_REG1 0x2004
26 #define RP_TX_CNTRL 0x2008
27 #define RP_TX_EOP 0x2
28 #define RP_TX_SOP 0x1
29 #define RP_RXCPL_STATUS 0x2010
30 #define RP_RXCPL_EOP 0x2
31 #define RP_RXCPL_SOP 0x1
32 #define RP_RXCPL_REG0 0x2014
33 #define RP_RXCPL_REG1 0x2018
[all …]
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pcie-altera.c | 23 #define RP_TX_REG0 0x2000
24 #define RP_TX_REG1 0x2004
25 #define RP_TX_CNTRL 0x2008
26 #define RP_TX_EOP 0x2
27 #define RP_TX_SOP 0x1
28 #define RP_RXCPL_STATUS 0x2010
29 #define RP_RXCPL_EOP 0x2
30 #define RP_RXCPL_SOP 0x1
31 #define RP_RXCPL_REG0 0x2014
32 #define RP_RXCPL_REG1 0x2018
[all …]
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| /kernel/linux/linux-6.6/drivers/scsi/qla2xxx/ |
| D | qla_dbg.c | 13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
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| /kernel/linux/linux-5.10/drivers/scsi/qla2xxx/ |
| D | qla_dbg.c | 13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x210e-0x2115 |
16 * | | | 0x211c-0x2128 |
17 * | | | 0x212c-0x2134 |
18 * | Queue Command and IO tracing | 0x3074 | 0x300b |
19 * | | | 0x3027-0x3028 |
20 * | | | 0x303d-0x3041 |
21 * | | | 0x302e,0x3033 |
22 * | | | 0x3036,0x3038 |
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_reg.h | 10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_reg.h | 10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | wm8997.c | 37 static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
38 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
39 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
40 static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
41 static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
44 { 0x301D, 0x7B15 },
45 { 0x301B, 0x0050 },
46 { 0x305D, 0x7B17 },
47 { 0x305B, 0x0050 },
48 { 0x3001, 0x08FE },
[all …]
|