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/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dintel,cgu-lgm.yaml42 reg = <0xe0200000 0x33c>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dintel,cgu-lgm.yaml42 reg = <0xe0200000 0x33c>;
/kernel/linux/linux-6.6/drivers/net/wireless/quantenna/qtnfmac/pcie/
Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/quantenna/qtnfmac/pcie/
Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0)
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4)
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310)
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319)
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c)
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324)
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/
Dunimac.h5 #define UMAC_HD_BKP_CTRL 0x004
6 #define HD_FC_EN (1 << 0)
9 #define IPG_CONFIG_RX_MASK 0x1F
10 #define UMAC_CMD 0x008
11 #define CMD_TX_EN (1 << 0)
13 #define CMD_SPEED_10 0
38 #define UMAC_MAC0 0x00c
39 #define UMAC_MAC1 0x010
40 #define UMAC_MAX_FRAME_LEN 0x014
41 #define UMAC_PAUSE_QUANTA 0x018
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/kernel/linux/linux-5.10/drivers/media/radio/
Dradio-cadet.c57 module_param(io, int, 0);
58 MODULE_PARM_DESC(io, "I/O address of Cadet card (0x330,0x332,0x334,0x336,0x338,0x33a,0x33c,0x33e)");
59 module_param(radio_nr, int, 0);
96 .index = 0,
123 if ((inb(dev->io + 1) & 0x40) == 0) in cadet_getstereo()
131 unsigned fifo = 0; in cadet_gettune()
139 outb(0x00, dev->io + 1); /* Ensure WRITE-ENABLE is LOW */ in cadet_gettune()
140 dev->tunestat = 0xffff; in cadet_gettune()
145 for (i = 0; i < 25; i++) { in cadet_gettune()
146 fifo = (fifo << 1) | ((inb(dev->io + 1) >> 7) & 0x01); in cadet_gettune()
[all …]
/kernel/linux/linux-6.6/drivers/media/radio/
Dradio-cadet.c57 module_param(io, int, 0);
58 MODULE_PARM_DESC(io, "I/O address of Cadet card (0x330,0x332,0x334,0x336,0x338,0x33a,0x33c,0x33e)");
59 module_param(radio_nr, int, 0);
96 .index = 0,
123 if ((inb(dev->io + 1) & 0x40) == 0) in cadet_getstereo()
131 unsigned fifo = 0; in cadet_gettune()
139 outb(0x00, dev->io + 1); /* Ensure WRITE-ENABLE is LOW */ in cadet_gettune()
140 dev->tunestat = 0xffff; in cadet_gettune()
145 for (i = 0; i < 25; i++) { in cadet_gettune()
146 fifo = (fifo << 1) | ((inb(dev->io + 1) >> 7) & 0x01); in cadet_gettune()
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Drtl2832.c14 [DVBT_SOFT_RST] = {0x101, 2, 2},
15 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
16 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
17 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
18 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
19 [DVBT_AD_EN_REG] = {0x008, 7, 7},
20 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
21 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
22 [DVBT_MGD_THD0] = {0x195, 7, 0},
23 [DVBT_MGD_THD1] = {0x196, 7, 0},
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Drtl2832.c14 [DVBT_SOFT_RST] = {0x101, 2, 2},
15 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
16 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
17 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
18 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
19 [DVBT_AD_EN_REG] = {0x008, 7, 7},
20 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
21 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
22 [DVBT_MGD_THD0] = {0x195, 7, 0},
23 [DVBT_MGD_THD1] = {0x196, 7, 0},
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/mediatek/
Dmtk_ppe_regs.h7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/via/
Dvia-camera.h5 #define VCR_INTCTRL 0x300 /* Capture interrupt control */
6 #define VCR_IC_EAV 0x0001 /* End of active video status */
7 #define VCR_IC_EVBI 0x0002 /* End of VBI status */
8 #define VCR_IC_FBOTFLD 0x0004 /* "flipping" Bottom field is active */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
10 #define VCR_IC_VSYNC 0x0020 /* 0 = VB, 1 = active video */
11 #define VCR_IC_BOTFLD 0x0040 /* Bottom field is active */
12 #define VCR_IC_FFULL 0x0080 /* FIFO full */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/
Dvia-camera.h5 #define VCR_INTCTRL 0x300 /* Capture interrupt control */
6 #define VCR_IC_EAV 0x0001 /* End of active video status */
7 #define VCR_IC_EVBI 0x0002 /* End of VBI status */
8 #define VCR_IC_FBOTFLD 0x0004 /* "flipping" Bottom field is active */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
10 #define VCR_IC_VSYNC 0x0020 /* 0 = VB, 1 = active video */
11 #define VCR_IC_BOTFLD 0x0040 /* Bottom field is active */
12 #define VCR_IC_FFULL 0x0080 /* FIFO full */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
[all …]
/kernel/linux/linux-6.6/drivers/pmdomain/mediatek/
Dmt8183-pm-domains.h17 .ctl_offs = 0x0314,
18 .pwr_sta_offs = 0x0180,
19 .pwr_sta2nd_offs = 0x0184,
26 .ctl_offs = 0x032c,
27 .pwr_sta_offs = 0x0180,
28 .pwr_sta2nd_offs = 0x0184,
29 .sram_pdn_bits = 0,
30 .sram_pdn_ack_bits = 0,
39 .ctl_offs = 0x0334,
40 .pwr_sta_offs = 0x0180,
[all …]

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