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/kernel/linux/linux-6.6/include/linux/mfd/wm8350/
Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm8350/
Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/loongson/
Dloongson,ls2k-pmc.yaml65 reg = <0x1fe27000 0x58>;
68 loongson,suspend-address = <0x0 0x1c000500>;
72 offset = <0x30>;
73 mask = <0x1>;
79 offset = <0x14>;
80 mask = <0x3c00>;
81 value = <0x3c00>;
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/
Dlantiq_pce.h11 OUT_MAC0 = 0,
55 #define INSTR 0
61 FLAG_ITAG = 0,
89 MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
90 MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
91 MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
92 MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
93 MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
94 MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
95 MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/
Dlantiq_pce.h11 OUT_MAC0 = 0,
55 #define INSTR 0
61 FLAG_ITAG = 0,
89 MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
90 MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
91 MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
92 MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
93 MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
94 MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
95 MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1b
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Drt700.h33 #define RT700_AUDIO_FUNCTION_GROUP 0x01
34 #define RT700_DAC_OUT1 0x02
35 #define RT700_DAC_OUT2 0x03
36 #define RT700_ADC_IN1 0x09
37 #define RT700_ADC_IN2 0x08
38 #define RT700_DMIC1 0x12
39 #define RT700_DMIC2 0x13
40 #define RT700_SPK_OUT 0x14
41 #define RT700_MIC2 0x19
42 #define RT700_LINE1 0x1a
[all …]
Drt715.h32 #define RT715_AUDIO_FUNCTION_GROUP 0x01
33 #define RT715_MIC_ADC 0x07
34 #define RT715_LINE_ADC 0x08
35 #define RT715_MIX_ADC 0x09
36 #define RT715_DMIC1 0x12
37 #define RT715_DMIC2 0x13
38 #define RT715_MIC1 0x18
39 #define RT715_MIC2 0x19
40 #define RT715_LINE1 0x1a
41 #define RT715_LINE2 0x1b
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
/kernel/linux/linux-6.6/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/kernel/linux/linux-5.10/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/kernel/linux/linux-6.6/arch/sh/boards/
Dboard-magicpanelr2.c33 #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
43 for (i = 0; i < 10; ++i) { in ethernet_reset_finished()
49 return 0; in ethernet_reset_finished()
55 CLRBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
60 SETBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
65 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
67 __raw_writel(0x36db0400, CS2BCR); in setup_chip_select()
69 __raw_writel(0x000003c0, CS2WCR); in setup_chip_select()
71 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
73 __raw_writel(0x00000200, CS4BCR); in setup_chip_select()
[all …]
/kernel/linux/linux-5.10/arch/sh/boards/
Dboard-magicpanelr2.c32 #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
42 for (i = 0; i < 10; ++i) { in ethernet_reset_finished()
48 return 0; in ethernet_reset_finished()
54 CLRBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
59 SETBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
64 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
66 __raw_writel(0x36db0400, CS2BCR); in setup_chip_select()
68 __raw_writel(0x000003c0, CS2WCR); in setup_chip_select()
70 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
72 __raw_writel(0x00000200, CS4BCR); in setup_chip_select()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mgag200/
Dmgag200_drv.h33 #define DRIVER_MINOR 0
34 #define DRIVER_PATCHLEVEL 0
41 #define MGA_BIOS_OFFSET 0x7ffc
43 #define ATTR_INDEX 0x1fc0
44 #define ATTR_DATA 0x1fc1
60 } while (0)
64 RREG8(0x1fda); \
67 } while (0) \
73 } while (0) \
79 } while (0) \
[all …]
/kernel/linux/linux-6.6/drivers/w1/masters/
Dmatrox_w1.c32 #define MATROX_BASE 0x3C00
33 #define MATROX_STATUS 0x1e14
35 #define MATROX_PORT_INDEX_OFFSET 0x00
36 #define MATROX_PORT_DATA_OFFSET 0x0A
38 #define MATROX_GET_CONTROL 0x2A
39 #define MATROX_GET_DATA 0x2B
40 #define MATROX_CURSOR_CTL 0x06
90 bit = 0; in matrox_w1_write_ddc_bit()
96 matrox_w1_write_reg(dev, MATROX_GET_DATA, 0x00); in matrox_w1_write_ddc_bit()
111 matrox_w1_write_reg(dev, MATROX_GET_DATA, 0xFF); in matrox_w1_hw_init()
[all …]

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