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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-mpc.txt28 #size-cells = <0>;
30 reg = <0x1740 0x20>;
31 interrupts = <11 0x8>;
38 reg = <0x1760 0x8>;
44 #size-cells = <0>;
46 reg = <0x3d00 0x40>;
47 interrupts = <2 15 0>;
55 #size-cells = <0>;
57 reg = <0x3100 0x100>;
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_3_1_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_4_0_d.h26 #define ixUVD_CGC_CTRL2 0x00C1
27 #define ixUVD_CGC_MEM_CTRL 0x00C0
28 #define ixUVD_LMI_ADDR_EXT2 0x00AB
29 #define ixUVD_LMI_CACHE_CTRL 0x009B
30 #define ixUVD_LMI_SWAP_CNTL2 0x00AA
31 #define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048
32 #define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114
33 #define ixUVD_MIF_REF_ADDR_CONFIG 0x004C
34 #define mmUVD_CGC_CTRL 0x3D2C
35 #define mmUVD_CGC_GATE 0x3D2A
[all …]
Duvd_4_2_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_5_0_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_6_0_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_3_1_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_4_0_d.h26 #define ixUVD_CGC_CTRL2 0x00C1
27 #define ixUVD_CGC_MEM_CTRL 0x00C0
28 #define ixUVD_LMI_ADDR_EXT2 0x00AB
29 #define ixUVD_LMI_CACHE_CTRL 0x009B
30 #define ixUVD_LMI_SWAP_CNTL2 0x00AA
31 #define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048
32 #define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114
33 #define ixUVD_MIF_REF_ADDR_CONFIG 0x004C
34 #define mmUVD_CGC_CTRL 0x3D2C
35 #define mmUVD_CGC_GATE 0x3D2A
[all …]
Duvd_4_2_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_5_0_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
Duvd_6_0_d.h27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0
28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29 #define mmUVD_SEMA_CMD 0x3bc2
30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33 #define mmUVD_ENGINE_CNTL 0x3bc6
34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/
Di2c-mpc.yaml69 #size-cells = <0>;
71 reg = <0x1740 0x20>;
72 interrupts = <11 0x8>;
81 #size-cells = <0>;
83 reg = <0x3d00 0x40>;
84 interrupts = <2 15 0>;
93 #size-cells = <0>;
95 reg = <0x3100 0x100>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/kernel/linux/linux-5.10/drivers/scsi/
Ddpti.h66 #define DPT_ORGANIZATION_ID (0x1B) /* For Private Messages */
76 #define EMPTY_QUEUE 0xffffffff
77 #define I2O_INTERRUPT_PENDING_B (0x08)
79 #define PCI_DPT_VENDOR_ID (0x1044) // DPT PCI Vendor ID
80 #define PCI_DPT_DEVICE_ID (0xA501) // DPT PCI I2O Device ID
81 #define PCI_DPT_RAPTOR_DEVICE_ID (0xA511)
102 #define FOREVER (0)
113 #define I2O_SCSI_DEVICE_DSC_MASK 0x00FF
115 #define I2O_DETAIL_STATUS_UNSUPPORTED_FUNCTION 0x000A
117 #define I2O_SCSI_DSC_MASK 0xFF00
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mgag200/
Dmgag200_reg.h24 #define MGAREG_DWGCTL 0x1c00
25 #define MGAREG_MACCESS 0x1c04
27 #define MGAREG_MCTLWTST 0x1c08
28 #define MGAREG_ZORG 0x1c0c
30 #define MGAREG_PAT0 0x1c10
31 #define MGAREG_PAT1 0x1c14
32 #define MGAREG_PLNWT 0x1c1c
34 #define MGAREG_BCOL 0x1c20
35 #define MGAREG_FCOL 0x1c24
37 #define MGAREG_SRC0 0x1c30
[all …]

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