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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/imx/
Dimx8m-soc.yaml29 "^soc@[0-9a-f]+$":
76 soc@0 {
80 ranges = <0x0 0x0 0x0 0x3e000000>;
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/
Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/kernel/liteos_a/kernel/base/misc/
Dvm_shellcmd.c53 #define ARGC_0 0
72 if (len <= 2) { // pid range is 0~63, max pid string length is 2 in OsPid()
73 for (UINT32 i = 0; i < len; i++) { in OsPid()
74 if (isdigit(str[i]) == 0) { in OsPid()
87 "pid(0~63), print process[pid] vm address space information\n" in OsPrintUsage()
110 if (argc == 0) { in OsShellCmdDumpVm()
113 pid_t pid = OsPid(argv[0]); in OsShellCmdDumpVm()
114 if (strcmp(argv[0], "-a") == 0) { in OsShellCmdDumpVm()
116 } else if (strcmp(argv[0], "-k") == 0) { in OsShellCmdDumpVm()
118 } else if (pid >= 0) { in OsShellCmdDumpVm()
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dqcom-ipq8064-rb3011.dts23 reg = <0x42000000 0x3e000000>;
27 mdio0: mdio-0 {
31 <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
33 #size-cells = <0>;
35 pinctrl-0 = <&mdio0_pins>;
41 #size-cells = <0>;
43 dsa,member = <0 0>;
45 pinctrl-0 = <&sw0_reset_pin>;
49 reg = <0x10>;
53 #size-cells = <0>;
[all …]
Dbcm21664.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
44 secondary-boot-reg = <0x35004178>;
52 #address-cells = <0>;
54 reg = <0x3ff01000 0x1000>,
55 <0x3ff00100 0x100>;
60 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
66 reg = <0x3e000000 0x118>;
76 reg = <0x3e001000 0x118>;
[all …]
Dbcm11351.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
44 secondary-boot-reg = <0x3500417c>;
52 #address-cells = <0>;
54 reg = <0x3ff01000 0x1000>,
55 <0x3ff00100 0x100>;
60 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
66 reg = <0x3e000000 0x1000>;
76 reg = <0x3e001000 0x1000>;
[all …]
Dbcm23550.dtsi48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
61 secondary-boot-reg = <0x35004178>;
70 secondary-boot-reg = <0x35004178>;
79 secondary-boot-reg = <0x35004178>;
88 ranges = <0 0x34000000 0x102f83ac>;
94 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
99 reg = <0x01001f00 0x24>;
104 reg = <0x01003000 0x524>;
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/ibm/emac/
Dmal.h37 #define MAL_CFG 0x00
38 #define MAL_CFG_SR 0x80000000
39 #define MAL_CFG_PLBB 0x00004000
40 #define MAL_CFG_OPBBL 0x00000080
41 #define MAL_CFG_EOPIE 0x00000004
42 #define MAL_CFG_LEA 0x00000002
43 #define MAL_CFG_SD 0x00000001
46 #define MAL1_CFG_PLBP_MASK 0x00c00000
47 #define MAL1_CFG_PLBP_10 0x00800000
48 #define MAL1_CFG_GA 0x00200000
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/ibm/emac/
Dmal.h37 #define MAL_CFG 0x00
38 #define MAL_CFG_SR 0x80000000
39 #define MAL_CFG_PLBB 0x00004000
40 #define MAL_CFG_OPBBL 0x00000080
41 #define MAL_CFG_EOPIE 0x00000004
42 #define MAL_CFG_LEA 0x00000002
43 #define MAL_CFG_SD 0x00000001
46 #define MAL1_CFG_PLBP_MASK 0x00c00000
47 #define MAL1_CFG_PLBP_10 0x00800000
48 #define MAL1_CFG_GA 0x00200000
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dqcom-ipq8064-rb3011.dts24 reg = <0x42000000 0x3e000000>;
28 mdio0: mdio-0 {
32 <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
34 #size-cells = <0>;
36 pinctrl-0 = <&mdio0_pins>;
42 dsa,member = <0 0>;
44 pinctrl-0 = <&sw0_reset_pin>;
48 reg = <0x10>;
52 #size-cells = <0>;
54 switch0cpu: port@0 {
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm21664.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 secondary-boot-reg = <0x35004178>;
41 #address-cells = <0>;
43 reg = <0x3ff01000 0x1000>,
44 <0x3ff00100 0x100>;
49 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
54 reg = <0x3e000000 0x118>;
64 reg = <0x3e001000 0x118>;
[all …]
Dbcm11351.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 secondary-boot-reg = <0x3500417c>;
41 #address-cells = <0>;
43 reg = <0x3ff01000 0x1000>,
44 <0x3ff00100 0x100>;
49 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
54 reg = <0x3e000000 0x1000>;
64 reg = <0x3e001000 0x1000>;
[all …]
Dbcm23550.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
60 secondary-boot-reg = <0x35004178>;
69 secondary-boot-reg = <0x35004178>;
78 secondary-boot-reg = <0x35004178>;
87 ranges = <0 0x34000000 0x102f83ac>;
93 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
98 reg = <0x01001f00 0x24>;
103 reg = <0x01003000 0x524>;
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Daiutils.c35 #define SCC_SS_MASK 0x00000007
37 #define SCC_SS_LPO 0x00000000
39 #define SCC_SS_XTAL 0x00000001
41 #define SCC_SS_PCI 0x00000002
42 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
43 #define SCC_LF 0x00000200
44 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
45 #define SCC_LP 0x00000400
46 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
47 #define SCC_FS 0x00000800
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Daiutils.c35 #define SCC_SS_MASK 0x00000007
37 #define SCC_SS_LPO 0x00000000
39 #define SCC_SS_XTAL 0x00000001
41 #define SCC_SS_PCI 0x00000002
42 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
43 #define SCC_LF 0x00000200
44 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
45 #define SCC_LP 0x00000400
46 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
47 #define SCC_FS 0x00000800
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp.dtsi43 #size-cells = <0>;
45 A53_0: cpu@0 {
48 reg = <0x0>;
59 reg = <0x1>;
70 reg = <0x2>;
81 reg = <0x3>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 #clock-cells = <0>;
117 #clock-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/hexagon/kernel/
Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]

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