Searched +full:0 +full:x3f00 (Results 1 – 25 of 251) sorted by relevance
1234567891011
11 #define _PSTX_MSK 0xF013 #define _PSRX_MSK 0x0F14 #define _PSRX_SHT 027 #define _RXFF0_EMPTY BIT(0)30 #define _BKQ_EMPTY_TH_MSK 0x0F000032 #define _BEQ_EMPTY_TH_MSK 0x00F00034 #define _VIQ_EMPTY_TH_MSK 0x000F0036 #define _VOQ_EMPTY_TH_MSK 0x0000F038 #define _BMCQ_EMPTY_TH_MSK 0x00000F39 #define _BMCQ_EMPTY_TH_SHT 0[all …]
23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 024 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F0028 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F000030 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F00000033 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 034 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F0038 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F000040 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000[all …]
23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 024 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F0028 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F000030 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F00000033 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 034 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F0038 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F000040 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000[all …]
23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 024 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F0028 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F000030 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F00000033 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 034 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F0038 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F000040 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000[all …]
23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 024 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x726 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x70028 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x7000030 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x700000033 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 034 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x736 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x70038 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x7000040 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000[all …]
23 #define MME_ARCH_STATUS_A_SHIFT 024 #define MME_ARCH_STATUS_A_MASK 0x126 #define MME_ARCH_STATUS_B_MASK 0x228 #define MME_ARCH_STATUS_CIN_MASK 0x430 #define MME_ARCH_STATUS_COUT_MASK 0x832 #define MME_ARCH_STATUS_TE_MASK 0x1034 #define MME_ARCH_STATUS_LD_MASK 0x2036 #define MME_ARCH_STATUS_ST_MASK 0x4038 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x8040 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100[all …]
12 #define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))14 #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))16 #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))18 #define TXMASK 0x3F00
13 #define CX18_AUDIO_ENABLE 0xc7201414 #define CX18_AI1_MUX_MASK 0x3015 #define CX18_AI1_MUX_I2S1 0x0016 #define CX18_AI1_MUX_I2S2 0x1017 #define CX18_AI1_MUX_843_I2S 0x2018 #define CX18_AI1_MUX_INVALID 0x3025 int ret = 0; in cx18_av_verifyfw()34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()35 dl_control |= 0x0f000000; in cx18_av_verifyfw()38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()[all …]
23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C0425 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C0827 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C1031 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D0035 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D2037 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D6039 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D6441 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68[all …]
35 #define CB710_MMC_DATA_PORT 0x0037 #define CB710_MMC_CONFIG_PORT 0x0438 #define CB710_MMC_CONFIG0_PORT 0x0439 #define CB710_MMC_CONFIG1_PORT 0x0540 #define CB710_MMC_C1_4BIT_DATA_BUS 0x4041 #define CB710_MMC_CONFIG2_PORT 0x0642 #define CB710_MMC_C2_READ_PIO_SIZE_MASK 0x0F /* N-1 */43 #define CB710_MMC_CONFIG3_PORT 0x0745 #define CB710_MMC_CONFIGB_PORT 0x0847 #define CB710_MMC_IRQ_ENABLE_PORT 0x0C[all …]
12 #define E1000_IVAR_VALID 0x8015 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */16 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */17 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */18 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */19 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */20 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */21 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */22 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */23 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */[all …]
27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x236 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1[all …]
11 #define RF_DATA 0x1d413 #define rPMAC_Reset 0x10014 #define rPMAC_TxStart 0x10415 #define rPMAC_TxLegacySIG 0x10816 #define rPMAC_TxHTSIG1 0x10c17 #define rPMAC_TxHTSIG2 0x11018 #define rPMAC_PHYDebug 0x11419 #define rPMAC_TxPacketNum 0x11820 #define rPMAC_TxIdle 0x11c21 #define rPMAC_TxMACHeader0 0x120[all …]
10 #define RF_DATA 0x1d412 #define rPMAC_Reset 0x10013 #define rPMAC_TxStart 0x10414 #define rPMAC_TxLegacySIG 0x10815 #define rPMAC_TxHTSIG1 0x10c16 #define rPMAC_TxHTSIG2 0x11017 #define rPMAC_PHYDebug 0x11418 #define rPMAC_TxPacketNum 0x11819 #define rPMAC_TxIdle 0x11c20 #define rPMAC_TxMACHeader0 0x120[all …]