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/kernel/linux/linux-6.6/sound/soc/fsl/
Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
Dfsl_audmix.c38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
53 { .tdms = 0, .clk = 0, .msg = "" },
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
63 { .tdms = 0, .clk = 0, .msg = "" },
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
73 { .tdms = 0, .clk = 0, .msg = "" },
75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
[all …]
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
Dfsl_audmix.c38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
53 { .tdms = 0, .clk = 0, .msg = "" },
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
63 { .tdms = 0, .clk = 0, .msg = "" },
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
73 { .tdms = 0, .clk = 0, .msg = "" },
75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/mxsfb/
Dmxsfb_regs.h15 #define LCDC_CTRL 0x00
16 #define LCDC_CTRL1 0x10
17 #define LCDC_V3_TRANSFER_COUNT 0x20
18 #define LCDC_V4_CTRL2 0x20
19 #define LCDC_V4_TRANSFER_COUNT 0x30
20 #define LCDC_V4_CUR_BUF 0x40
21 #define LCDC_V4_NEXT_BUF 0x50
22 #define LCDC_V3_CUR_BUF 0x30
23 #define LCDC_V3_NEXT_BUF 0x40
24 #define LCDC_VDCTRL0 0x70
[all …]
Dlcdif_regs.h15 #define LCDC_V8_CTRL 0x00
16 #define LCDC_V8_DISP_PARA 0x10
17 #define LCDC_V8_DISP_SIZE 0x14
18 #define LCDC_V8_HSYN_PARA 0x18
19 #define LCDC_V8_VSYN_PARA 0x1c
20 #define LCDC_V8_VSYN_HSYN_WIDTH 0x20
21 #define LCDC_V8_INT_STATUS_D0 0x24
22 #define LCDC_V8_INT_ENABLE_D0 0x28
23 #define LCDC_V8_INT_STATUS_D1 0x30
24 #define LCDC_V8_INT_ENABLE_D1 0x34
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mxsfb/
Dmxsfb_regs.h15 #define LCDC_CTRL 0x00
16 #define LCDC_CTRL1 0x10
17 #define LCDC_V3_TRANSFER_COUNT 0x20
18 #define LCDC_V4_CTRL2 0x20
19 #define LCDC_V4_TRANSFER_COUNT 0x30
20 #define LCDC_V4_CUR_BUF 0x40
21 #define LCDC_V4_NEXT_BUF 0x50
22 #define LCDC_V3_CUR_BUF 0x30
23 #define LCDC_V3_NEXT_BUF 0x40
24 #define LCDC_VDCTRL0 0x70
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]
Ddma_macro_masks.h23 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0
24 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF
27 #define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0
28 #define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF
31 #define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0
32 #define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF
35 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0
36 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF
39 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0
40 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF
[all …]
Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/goya/asic_reg/
Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]
Ddma_macro_masks.h23 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0
24 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF
27 #define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0
28 #define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF
31 #define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0
32 #define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF
35 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0
36 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF
39 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0
40 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF
[all …]
Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt6797/
Dmt6797-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/kernel/linux/linux-5.10/sound/soc/mediatek/mt6797/
Dmt6797-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/kernel/linux/linux-5.10/sound/soc/mediatek/mt8183/
Dmt8183-afe-pcm.c24 MTK_AFE_RATE_8K = 0,
43 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
50 MTK_AFE_PCM_RATE_8K = 0,
139 .fifo_size = 0,
149 int id = asoc_rtd_to_cpu(rtd, 0)->id; in mt8183_memif_fs()
294 I_ADDA_UL_CH1, 1, 0),
296 I_I2S0_CH1, 1, 0),
301 I_ADDA_UL_CH2, 1, 0),
303 I_I2S0_CH2, 1, 0),
308 I_ADDA_UL_CH1, 1, 0),
[all …]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8183/
Dmt8183-afe-pcm.c24 MTK_AFE_RATE_8K = 0,
43 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
50 MTK_AFE_PCM_RATE_8K = 0,
139 .fifo_size = 0,
149 int id = asoc_rtd_to_cpu(rtd, 0)->id; in mt8183_memif_fs()
294 I_ADDA_UL_CH1, 1, 0),
296 I_I2S0_CH1, 1, 0),
301 I_ADDA_UL_CH2, 1, 0),
303 I_I2S0_CH2, 1, 0),
308 I_ADDA_UL_CH1, 1, 0),
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dti,am3359-adc.yaml27 description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
37 the start of ADC conversion. Maximum value is 0x3FFFF.
45 to sample (to hold start of conversion high). Maximum value is 0xFF.
72 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
73 ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>;
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.h51 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
59 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.h47 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
55 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/touchscreen/
Dti-tsc-adc.txt30 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
31 XP = 0, XN = 1, YP = 2, YN = 3.
37 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
46 event. Start from a lower value, say 0x400, and
60 Maximum value is 0x3FFFF.
66 Maximum value is 0xFF.
71 by ADC to generate a sample. Valid range is 0
81 ti,wire-config = <0x00 0x11 0x22 0x33>;
82 ti,charge-delay = <0x400>;
87 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
[all …]

1234567891011