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/kernel/linux/linux-6.6/drivers/net/phy/
Dmediatek-ge.c6 #define MTK_EXT_PAGE_ACCESS 0x1f
7 #define MTK_PHY_PAGE_STANDARD 0x0000
8 #define MTK_PHY_PAGE_EXTENDED 0x0001
9 #define MTK_PHY_PAGE_EXTENDED_2 0x0002
10 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
11 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
12 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in mtk_gephy_config_init()
30 phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); in mtk_gephy_config_init()
34 __phy_write(phydev, 0x10, 0xafae); in mtk_gephy_config_init()
[all …]
/kernel/linux/linux-5.10/drivers/ide/
Dide-dma-sff.c28 return 0; in config_drive_for_dma()
33 * UltraDMA (mode 0/1/2/3/4/5/6) enabled in config_drive_for_dma()
36 ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f)) in config_drive_for_dma()
43 if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 || in config_drive_for_dma()
44 (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404) in config_drive_for_dma()
51 return 0; in config_drive_for_dma()
105 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
110 * returns 0 otherwise.
119 unsigned int count = 0; in ide_build_dmatable()
140 bcount = 0x10000 - (cur_addr & 0xffff); in ide_build_dmatable()
[all …]
/kernel/linux/linux-5.10/drivers/media/i2c/cx25840/
Dcx25840-vbi.c25 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in decode_vps()
26 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in decode_vps()
27 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, in decode_vps()
28 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, in decode_vps()
29 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, in decode_vps()
30 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, in decode_vps()
31 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in decode_vps()
32 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in decode_vps()
33 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, in decode_vps()
34 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, in decode_vps()
[all …]
/kernel/linux/linux-6.6/drivers/media/i2c/cx25840/
Dcx25840-vbi.c25 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in decode_vps()
26 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in decode_vps()
27 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, in decode_vps()
28 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, in decode_vps()
29 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, in decode_vps()
30 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, in decode_vps()
31 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in decode_vps()
32 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in decode_vps()
33 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, in decode_vps()
34 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, in decode_vps()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_utils.c20 #define HW_ATL_UCP_0X370_REG 0x0370U
22 #define HW_ATL_MIF_CMD 0x0200U
23 #define HW_ATL_MIF_ADDR 0x0208U
24 #define HW_ATL_MIF_VAL 0x020CU
26 #define HW_ATL_MPI_RPC_ADDR 0x0334U
27 #define HW_ATL_RPC_CONTROL_ADR 0x0338U
28 #define HW_ATL_RPC_STATE_ADR 0x033CU
30 #define HW_ATL_MPI_FW_VERSION 0x18
31 #define HW_ATL_MPI_CONTROL_ADR 0x0368U
32 #define HW_ATL_MPI_STATE_ADR 0x036CU
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_utils.c20 #define HW_ATL_UCP_0X370_REG 0x0370U
22 #define HW_ATL_MIF_CMD 0x0200U
23 #define HW_ATL_MIF_ADDR 0x0208U
24 #define HW_ATL_MIF_VAL 0x020CU
26 #define HW_ATL_MPI_RPC_ADDR 0x0334U
27 #define HW_ATL_RPC_CONTROL_ADR 0x0338U
28 #define HW_ATL_RPC_STATE_ADR 0x033CU
30 #define HW_ATL_MPI_FW_VERSION 0x18
31 #define HW_ATL_MPI_CONTROL_ADR 0x0368U
32 #define HW_ATL_MPI_STATE_ADR 0x036CU
[all …]
/kernel/linux/linux-5.10/drivers/usb/musb/
Domap2430.h15 #define OTG_REVISION 0x400
17 #define OTG_SYSCONFIG 0x404
19 # define FORCESTDBY (0 << MIDLEMODE)
24 # define FORCEIDLE (0 << SIDLEMODE)
30 # define AUTOIDLE (1 << 0)
32 #define OTG_SYSSTATUS 0x408
33 # define RESETDONE (1 << 0)
35 #define OTG_INTERFSEL 0x40c
37 # define PHYSEL 0 /* bit position */
38 # define UTMI_8BIT (0 << PHYSEL)
[all …]
/kernel/linux/linux-6.6/drivers/usb/musb/
Domap2430.h15 #define OTG_REVISION 0x400
17 #define OTG_SYSCONFIG 0x404
19 # define FORCESTDBY (0 << MIDLEMODE)
24 # define FORCEIDLE (0 << SIDLEMODE)
30 # define AUTOIDLE (1 << 0)
32 #define OTG_SYSSTATUS 0x408
33 # define RESETDONE (1 << 0)
35 #define OTG_INTERFSEL 0x40c
37 # define PHYSEL 0 /* bit position */
38 # define UTMI_8BIT (0 << PHYSEL)
[all …]
/kernel/linux/linux-6.6/drivers/media/pci/cx18/
Dcx18-av-vbi.c18 * 4 byte EAV code: 0xff 0x00 0x00 0xRP
20 * 3 byte Anc data preamble: 0x00 0xff 0xff
24 * 2 byte Internal DID: VBI-line-# 0x80
31 * 0xb0 (Task 0 VerticalBlank HorizontalBlank 0 0 0 0)
32 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank 0 0 0 0)
36 * 0x90 (Task 0 0 HorizontalBlank 0 0 0 0)
37 * 0xd0 (Task EvenField 0 HorizontalBlank 0 0 0 0)
40 * 0x91 (1 0 010 0 !ActiveLine AncDataPresent)
41 * 0x55 (0 1 010 2ndField !ActiveLine AncDataPresent)
44 static const u8 sliced_vbi_did[2] = { 0x91, 0x55 };
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-vbi.c18 * 4 byte EAV code: 0xff 0x00 0x00 0xRP
20 * 3 byte Anc data preamble: 0x00 0xff 0xff
24 * 2 byte Internal DID: VBI-line-# 0x80
31 * 0xb0 (Task 0 VerticalBlank HorizontalBlank 0 0 0 0)
32 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank 0 0 0 0)
36 * 0x90 (Task 0 0 HorizontalBlank 0 0 0 0)
37 * 0xd0 (Task EvenField 0 HorizontalBlank 0 0 0 0)
40 * 0x91 (1 0 010 0 !ActiveLine AncDataPresent)
41 * 0x55 (0 1 010 2ndField !ActiveLine AncDataPresent)
44 static const u8 sliced_vbi_did[2] = { 0x91, 0x55 };
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0
[all …]
/kernel/linux/linux-6.6/sound/soc/tegra/
Dtegra210_mixer.h13 #define TEGRA210_MIXER_RX1_SOFT_RESET 0x04
14 #define TEGRA210_MIXER_RX1_STATUS 0x10
15 #define TEGRA210_MIXER_RX1_CIF_CTRL 0x24
16 #define TEGRA210_MIXER_RX1_CTRL 0x28
17 #define TEGRA210_MIXER_RX1_PEAK_CTRL 0x2c
18 #define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30
21 #define TEGRA210_MIXER_TX1_ENABLE 0x280
22 #define TEGRA210_MIXER_TX1_SOFT_RESET 0x284
23 #define TEGRA210_MIXER_TX1_STATUS 0x290
24 #define TEGRA210_MIXER_TX1_INT_STATUS 0x294
[all …]
/kernel/linux/linux-5.10/drivers/usb/host/
Dehci-fsl.h9 #define FSL_SOC_USB_SBUSCFG 0x90
10 #define SBUSCFG_INCR8 0x02 /* INCR8, specified */
11 #define FSL_SOC_USB_ULPIVP 0x170
12 #define FSL_SOC_USB_PORTSC1 0x184
14 #define PORT_PTS_UTMI (0<<30)
18 #define FSL_SOC_USB_PORTSC2 0x188
19 #define FSL_SOC_USB_USBMODE 0x1a8
20 #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
21 #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
24 #define FSL_SOC_USB_USBGENCTRL 0x200
[all …]
/kernel/linux/linux-6.6/drivers/usb/host/
Dehci-fsl.h9 #define FSL_SOC_USB_SBUSCFG 0x90
10 #define SBUSCFG_INCR8 0x02 /* INCR8, specified */
11 #define FSL_SOC_USB_ULPIVP 0x170
12 #define FSL_SOC_USB_PORTSC1 0x184
14 #define PORT_PTS_UTMI (0<<30)
18 #define FSL_SOC_USB_PORTSC2 0x188
19 #define FSL_SOC_USB_USBMODE 0x1a8
20 #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
21 #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
24 #define FSL_SOC_USB_USBGENCTRL 0x200
[all …]
/kernel/linux/linux-6.6/arch/m68k/coldfire/
Ddma_timer.c18 #define DMA_TIMER_0 (0x00)
19 #define DMA_TIMER_1 (0x40)
20 #define DMA_TIMER_2 (0x80)
21 #define DMA_TIMER_3 (0xc0)
23 #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
24 #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
25 #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
26 #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
27 #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
28 #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
[all …]
/kernel/linux/linux-5.10/arch/m68k/coldfire/
Ddma_timer.c18 #define DMA_TIMER_0 (0x00)
19 #define DMA_TIMER_1 (0x40)
20 #define DMA_TIMER_2 (0x80)
21 #define DMA_TIMER_3 (0xc0)
23 #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
24 #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
25 #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
26 #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
27 #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
28 #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/
Dnvmem.yaml24 pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$"
42 when it's driven low (logical '0') to allow writing.
46 "^.*@[0-9a-f]+$":
59 - minimum: 0
79 reg = <0x00700000 0x100000>;
87 reg = <0x404 0x10>;
91 reg = <0x504 0x11>;
96 reg = <0x6 0x2>;
101 reg = <0xc 0x1>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Dnvmem.yaml39 when it's driven low (logical '0') to allow writing.
50 "@[0-9a-f]+(,[0-7])?$":
68 reg = <0x00700000 0x100000>;
81 reg = <0x404 0x10>;
85 reg = <0x504 0x11>;
90 reg = <0x6 0x2>;
95 reg = <0xc 0x1>;
/kernel/linux/linux-5.10/drivers/hwspinlock/
Dsirf_hwspinlock.c30 #define HW_SPINLOCK_BASE 0x404
31 #define HW_SPINLOCK_OFFSET(x) (HW_SPINLOCK_BASE + 0x4 * (x))
45 /* release the lock by writing 0 to it */ in sirf_hwspinlock_unlock()
46 writel(0, lock_addr); in sirf_hwspinlock_unlock()
71 hwspin->io_base = devm_platform_ioremap_resource(pdev, 0); in sirf_hwspinlock_probe()
75 for (idx = 0; idx < HW_SPINLOCK_NUMBER; idx++) { in sirf_hwspinlock_probe()
83 &sirf_hwspinlock_ops, 0, in sirf_hwspinlock_probe()
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dtsi108.h18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
[all …]

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