| /kernel/linux/linux-5.10/drivers/media/pci/meye/ |
| D | meye.c | 55 MODULE_PARM_DESC(video_nr, "video device to register (0=/dev/video0, etc)");
71 memset(mem, 0, size); in rvmalloc()
73 while (size > 0) { in rvmalloc()
88 while ((long) size > 0) { in rvfree()
108 memset(meye.mchip_ptable, 0, sizeof(meye.mchip_ptable)); in ptable_alloc()
119 meye.mchip_dmahandle = 0; in ptable_alloc()
124 for (i = 0; i < MCHIP_NB_PAGES; i++) { in ptable_alloc()
133 for (j = 0; j < i; ++j) { in ptable_alloc()
145 meye.mchip_dmahandle = 0; in ptable_alloc()
151 return 0; in ptable_alloc()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | dra72x.dtsi | 27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
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| D | dra74x.dtsi | 49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | dra72x.dtsi | 27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
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| D | dra74x.dtsi | 49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
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| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | ptrace.h | 11 #define PTRACE_TRACEME 0
27 /* 0x4200-0x4300 are reserved for architecture-independent additions. */
28 #define PTRACE_SETOPTIONS 0x4200
29 #define PTRACE_GETEVENTMSG 0x4201
30 #define PTRACE_GETSIGINFO 0x4202
31 #define PTRACE_SETSIGINFO 0x4203
50 #define PTRACE_GETREGSET 0x4204
51 #define PTRACE_SETREGSET 0x4205
53 #define PTRACE_SEIZE 0x4206
54 #define PTRACE_INTERRUPT 0x4207
[all …]
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| /kernel/linux/linux-5.10/drivers/dma/ti/ |
| D | k3-psil-am654.c | 54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
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| /kernel/linux/linux-6.6/drivers/dma/ti/ |
| D | k3-psil-am654.c | 54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
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| D | k3-psil-am62.c | 73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4300),
79 PSIL_PDMA_XY_PKT(0x4301),
80 PSIL_PDMA_XY_PKT(0x4302),
81 PSIL_PDMA_XY_PKT(0x4303),
82 PSIL_PDMA_XY_PKT(0x4304),
83 PSIL_PDMA_XY_PKT(0x4305),
[all …]
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| D | k3-psil-am62a.c | 83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
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| D | k3-psil-am64.c | 66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-fs4.dtsi | 37 ranges = <0x0 0x0 0x67000000 0x00800000>;
39 crypto_mbox: crypto_mbox@0 {
41 reg = <0x00000000 0x200000>;
42 msi-parent = <&gic_its 0x4100>;
49 reg = <0x00400000 0x200000>;
51 msi-parent = <&gic_its 0x4300>;
55 raid0: raid@0 {
57 mboxes = <&raid_mbox 0 0x1 0xff00>,
58 <&raid_mbox 1 0x1 0xff00>,
59 <&raid_mbox 2 0x1 0xff00>,
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-fs4.dtsi | 37 ranges = <0x0 0x0 0x67000000 0x00800000>;
39 crypto_mbox: crypto_mbox@0 {
41 reg = <0x00000000 0x200000>;
42 msi-parent = <&gic_its 0x4100>;
49 reg = <0x00400000 0x200000>;
51 msi-parent = <&gic_its 0x4300>;
55 raid0: raid@0 {
57 mboxes = <&raid_mbox 0 0x1 0xff00>,
58 <&raid_mbox 1 0x1 0xff00>,
59 <&raid_mbox 2 0x1 0xff00>,
[all …]
|
| /kernel/linux/linux-6.6/include/uapi/linux/ |
| D | ptrace.h | 11 #define PTRACE_TRACEME 0
27 /* 0x4200-0x4300 are reserved for architecture-independent additions. */
28 #define PTRACE_SETOPTIONS 0x4200
29 #define PTRACE_GETEVENTMSG 0x4201
30 #define PTRACE_GETSIGINFO 0x4202
31 #define PTRACE_SETSIGINFO 0x4203
50 #define PTRACE_GETREGSET 0x4204
51 #define PTRACE_SETREGSET 0x4205
53 #define PTRACE_SEIZE 0x4206
54 #define PTRACE_INTERRUPT 0x4207
[all …]
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| /kernel/linux/linux-6.6/drivers/regulator/ |
| D | qcom_spmi-regulator.c | 25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | dcr-regs.h | 29 #define DCRN_CPR0_CONFIG_ADDR 0xc
30 #define DCRN_CPR0_CONFIG_DATA 0xd
33 #define DCRN_SDR0_CONFIG_ADDR 0xe
34 #define DCRN_SDR0_CONFIG_DATA 0xf
36 #define SDR0_PFC0 0x4100
37 #define SDR0_PFC1 0x4101
38 #define SDR0_PFC1_EPS 0x1c00000
40 #define SDR0_PFC1_RMII 0x02000000
41 #define SDR0_MFR 0x4300
42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | dcr-regs.h | 29 #define DCRN_CPR0_CONFIG_ADDR 0xc
30 #define DCRN_CPR0_CONFIG_DATA 0xd
33 #define DCRN_SDR0_CONFIG_ADDR 0xe
34 #define DCRN_SDR0_CONFIG_DATA 0xf
36 #define SDR0_PFC0 0x4100
37 #define SDR0_PFC1 0x4101
38 #define SDR0_PFC1_EPS 0x1c00000
40 #define SDR0_PFC1_RMII 0x02000000
41 #define SDR0_MFR 0x4300
42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | ti,icssg-prueth.yaml | 34 - const: tx0-0
38 - const: tx1-0
81 const: 0
84 ^port@[0-1]$:
93 - enum: [0, 1]
113 - port@0
131 /* Example k3-am654 base board SR2.0, dual-emac */
135 pinctrl-0 = <&icssg2_rgmii_pins_default>;
152 dmas = <&main_udmap 0xc300>, /* egress slice 0 */
153 <&main_udmap 0xc301>, /* egress slice 0 */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/reg_srcs/ |
| D | rv515 | 1 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/reg_srcs/ |
| D | rv515 | 1 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | broadsheetfb.c | 68 .sdcfg = (67 | (0 << 8) | (0 << 9) | (0 << 10) | (0 << 12)),
71 .fsynclen = 0,
80 .sdcfg = (100 | (1 << 8) | (1 << 9) | (0 << 10) | (0 << 12)),
83 .fsynclen = 0,
98 .xpanstep = 0,
99 .ypanstep = 0,
100 .ywrapstep = 0,
112 .red = { 0, 4, 0 },
113 .green = { 0, 4, 0 },
114 .blue = { 0, 4, 0 },
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | broadsheetfb.c | 68 .sdcfg = (67 | (0 << 8) | (0 << 9) | (0 << 10) | (0 << 12)),
71 .fsynclen = 0,
80 .sdcfg = (100 | (1 << 8) | (1 << 9) | (0 << 10) | (0 << 12)),
83 .fsynclen = 0,
98 .xpanstep = 0,
99 .ypanstep = 0,
100 .ywrapstep = 0,
112 .red = { 0, 4, 0 },
113 .green = { 0, 4, 0 },
114 .blue = { 0, 4, 0 },
[all …]
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| /kernel/linux/linux-5.10/drivers/regulator/ |
| D | qcom_spmi-regulator.c | 24 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
32 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | ov5645.c | 37 #define OV5645_SYSTEM_CTRL0 0x3008
38 #define OV5645_SYSTEM_CTRL0_START 0x02
39 #define OV5645_SYSTEM_CTRL0_STOP 0x42
40 #define OV5645_CHIP_ID_HIGH 0x300a
41 #define OV5645_CHIP_ID_HIGH_BYTE 0x56
42 #define OV5645_CHIP_ID_LOW 0x300b
43 #define OV5645_CHIP_ID_LOW_BYTE 0x45
44 #define OV5645_IO_MIPI_CTRL00 0x300e
45 #define OV5645_PAD_OUTPUT00 0x3019
46 #define OV5645_AWB_MANUAL_CONTROL 0x3406
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ov5645.c | 35 #define OV5645_SYSTEM_CTRL0 0x3008
36 #define OV5645_SYSTEM_CTRL0_START 0x02
37 #define OV5645_SYSTEM_CTRL0_STOP 0x42
38 #define OV5645_CHIP_ID_HIGH 0x300a
39 #define OV5645_CHIP_ID_HIGH_BYTE 0x56
40 #define OV5645_CHIP_ID_LOW 0x300b
41 #define OV5645_CHIP_ID_LOW_BYTE 0x45
42 #define OV5645_IO_MIPI_CTRL00 0x300e
43 #define OV5645_PAD_OUTPUT00 0x3019
44 #define OV5645_AWB_MANUAL_CONTROL 0x3406
[all …]
|