| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-imx8mp.c | 546 clk_hw_set_rate_range(hws[constr->clkid], 0, constr->maxrate); in imx8mp_clocks_apply_constraints()
558 anatop_base = devm_of_iomap(dev, np, 0, NULL); in imx8mp_clocks_probe()
564 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
575 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
583 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
584 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
585 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
586 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
587 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
588 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
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| D | clk-imx8mn.c | 334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe()
353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
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| D | clk-imx8mm.c | 314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
323 base = of_iomap(np, 0); in imx8mm_clocks_probe()
328 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
329 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
330 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
331 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
332 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
333 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
334 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
335 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
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| D | clk-imx8mq.c | 298 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
308 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe()
315 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
316 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
317 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
318 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
319 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
320 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe()
321 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
322 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | brcm,systemport.txt | 32 reg = <0xf04a0000 0x4650>;
34 fixed-link = <0 1 1000 0 0>;
36 interrupts = <0x0 0x16 0x0>,
37 <0x0 0x17 0x0>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | brcm,systemport.yaml | 77 reg = <0xf04a0000 0x4650>;
80 interrupts = <0x0 0x16 0x0>,
81 <0x0 0x17 0x0>;
|
| /kernel/linux/linux-6.6/sound/usb/line6/ |
| D | variax.c | 55 0xf0, 0x7e, 0x7f, 0x06, 0x02, 0x00, 0x01, 0x0c,
56 0x07, 0x00, 0x00, 0x00
63 0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x6b
67 0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x2a, 0x01,
68 0xf7
119 switch (buf[0]) { in line6_variax_process_message()
126 sizeof(variax_init_version) - 1) == 0) { in line6_variax_process_message()
134 sizeof(variax_init_done) - 1) == 0) { in line6_variax_process_message()
139 schedule_delayed_work(&line6->startup_work, 0); in line6_variax_process_message()
177 return 0; in variax_init()
[all …]
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| D | pod.c | 24 #define POD_NAME_OFFSET 0
30 #define POD_CONTROL_SIZE 0x80
80 POD_SYSEX_SAVE = 0x24,
81 POD_SYSEX_SYSTEM = 0x56,
82 POD_SYSEX_SYSTEMREQ = 0x57,
83 /* POD_SYSEX_UPDATE = 0x6c, */ /* software update! */
84 POD_SYSEX_STORE = 0x71,
85 POD_SYSEX_FINISH = 0x72,
86 POD_SYSEX_DUMPMEM = 0x73,
87 POD_SYSEX_DUMP = 0x74,
[all …]
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| /kernel/linux/linux-5.10/sound/usb/line6/ |
| D | variax.c | 55 0xf0, 0x7e, 0x7f, 0x06, 0x02, 0x00, 0x01, 0x0c,
56 0x07, 0x00, 0x00, 0x00
63 0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x6b
67 0xf0, 0x00, 0x01, 0x0c, 0x07, 0x00, 0x2a, 0x01,
68 0xf7
119 switch (buf[0]) { in line6_variax_process_message()
126 sizeof(variax_init_version) - 1) == 0) { in line6_variax_process_message()
134 sizeof(variax_init_done) - 1) == 0) { in line6_variax_process_message()
139 schedule_delayed_work(&line6->startup_work, 0); in line6_variax_process_message()
177 return 0; in variax_init()
[all …]
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| D | pod.c | 24 #define POD_NAME_OFFSET 0
30 #define POD_CONTROL_SIZE 0x80
80 POD_SYSEX_SAVE = 0x24,
81 POD_SYSEX_SYSTEM = 0x56,
82 POD_SYSEX_SYSTEMREQ = 0x57,
83 /* POD_SYSEX_UPDATE = 0x6c, */ /* software update! */
84 POD_SYSEX_STORE = 0x71,
85 POD_SYSEX_FINISH = 0x72,
86 POD_SYSEX_DUMPMEM = 0x73,
87 POD_SYSEX_DUMP = 0x74,
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/reg_srcs/ |
| D | rv515 | 1 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| D | r300 | 1 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| D | rs600 | 1 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| D | r420 | 1 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/reg_srcs/ |
| D | rv515 | 1 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| D | r300 | 1 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
|
| D | rs600 | 1 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| D | r420 | 1 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/renesas/ |
| D | rswitch.h | 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
23 for (i--; i >= 0; i--) \
43 #define RSWITCH_TOP_OFFSET 0x00008000
44 #define RSWITCH_COMA_OFFSET 0x00009000
45 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
46 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
47 #define RSWITCH_GWCA0_OFFSET 0x00010000
48 #define RSWITCH_GWCA1_OFFSET 0x00012000
54 #define GWCA_INDEX 0
56 #define GWCA_IPV_NUM 0
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx8mn.c | 302 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
311 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
318 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
319 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
320 …hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
321 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
322 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
323 …hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
324 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
325 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
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| D | clk-imx8mm.c | 309 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
318 base = of_iomap(np, 0); in imx8mm_clocks_probe()
323 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
324 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
325 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
326 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
327 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
328 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
329 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
330 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
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| D | clk-imx8mq.c | 290 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
300 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe()
307 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
308 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
309 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
310 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
311 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
312 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe()
313 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
314 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/ |
| D | rtw8852a.c | 15 #define RTW8852A_FW_FORMAT_MAX 0
21 {128, 1896, grp_0}, /* ACH 0 */
33 {40, 0, 0} /* FWCMDQ */
37 1896, /* Group 0 */
40 0 /* WP threshold */
69 {0x44AC, 0x00000000},
70 {0x44B0, 0x00000000},
71 {0x44B4, 0x00000000},
72 {0x44B8, 0x00000000},
73 {0x44BC, 0x00000000},
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | me4000.c | 46 #define ME4000_AO_CHAN(x) ((x) * 0x18)
48 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
49 #define ME4000_AO_CTRL_MODE_0 BIT(0)
59 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
60 #define ME4000_AO_STATUS_FSM BIT(0)
64 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
65 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
66 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
67 #define ME4000_AI_CTRL_REG 0x74
68 #define ME4000_AI_STATUS_REG 0x74
[all …]
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| /kernel/linux/linux-6.6/drivers/comedi/drivers/ |
| D | me4000.c | 45 #define ME4000_AO_CHAN(x) ((x) * 0x18)
47 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
48 #define ME4000_AO_CTRL_MODE_0 BIT(0)
58 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
59 #define ME4000_AO_STATUS_FSM BIT(0)
63 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
64 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
65 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
66 #define ME4000_AI_CTRL_REG 0x74
67 #define ME4000_AI_STATUS_REG 0x74
[all …]
|