| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx7ulp.c | 60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7ulp_clk_scg1_init()
69 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
73 …hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
74 …hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
77 …hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()
78 …hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()
81 hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4("apll", "apll_pre_div", base + 0x500); in imx7ulp_clk_scg1_init()
82 hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base + 0x600); in imx7ulp_clk_scg1_init()
85 hws[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0); in imx7ulp_clk_scg1_init()
86 hws[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2("apll_pfd1", "apll", base + 0x50c, 1); in imx7ulp_clk_scg1_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-imx7ulp.c | 60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7ulp_clk_scg1_init()
69 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
73 …hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
74 …hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
77 …hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()
78 …hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()
81 …hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500… in imx7ulp_clk_scg1_init()
82 …hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600… in imx7ulp_clk_scg1_init()
85 …IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c, 0); in imx7ulp_clk_scg1_init()
86 …hws[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/socionext/ |
| D | phy-uniphier-usb2.c | 18 #define SG_USBPHY1CTRL 0x500
19 #define SG_USBPHY1CTRL2 0x504
20 #define SG_USBPHY2CTRL 0x508
21 #define SG_USBPHY2CTRL2 0x50c /* LD11 */
22 #define SG_USBPHY12PLL 0x50c /* Pro4 */
23 #define SG_USBPHY3CTRL 0x510
24 #define SG_USBPHY3CTRL2 0x514
25 #define SG_USBPHY4CTRL 0x518 /* Pro4 */
26 #define SG_USBPHY4CTRL2 0x51c /* Pro4 */
27 #define SG_USBPHY34PLL 0x51c /* Pro4 */
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/socionext/ |
| D | phy-uniphier-usb2.c | 18 #define SG_USBPHY1CTRL 0x500
19 #define SG_USBPHY1CTRL2 0x504
20 #define SG_USBPHY2CTRL 0x508
21 #define SG_USBPHY2CTRL2 0x50c /* LD11 */
22 #define SG_USBPHY12PLL 0x50c /* Pro4 */
23 #define SG_USBPHY3CTRL 0x510
24 #define SG_USBPHY3CTRL2 0x514
25 #define SG_USBPHY4CTRL 0x518 /* Pro4 */
26 #define SG_USBPHY4CTRL2 0x51c /* Pro4 */
27 #define SG_USBPHY34PLL 0x51c /* Pro4 */
[all …]
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| /kernel/linux/linux-6.6/drivers/memory/tegra/ |
| D | tegra210-mc.h | 12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
[all …]
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra210-mc.h | 12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/ |
| D | phydm_reg.h | 17 #define ODM_EDCA_VO_PARAM 0x500
18 #define ODM_EDCA_VI_PARAM 0x504
19 #define ODM_EDCA_BE_PARAM 0x508
20 #define ODM_EDCA_BK_PARAM 0x50C
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| D | gk20a.c | 29 #define BUSY_SLOT 0
55 return nvkm_clk_astate(clk, *state, 0, false); in gk20a_pmu_dvfs_target()
82 level = max(0, level); in gk20a_pmu_dvfs_get_target_state()
100 status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
101 status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
109 nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
110 nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
125 u32 utilization = 0; in gk20a_pmu_dvfs_work()
161 nvkm_timer_alarm(pmu->subdev.device->timer, 0, &gpmu->alarm); in gk20a_pmu_fini()
182 nvkm_falcon_wr32(falcon, 0x504 + (BUSY_SLOT * 0x10), 0x00200001); in gk20a_pmu_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| D | gk20a.c | 29 #define BUSY_SLOT 0
55 return nvkm_clk_astate(clk, *state, 0, false); in gk20a_pmu_dvfs_target()
82 level = max(0, level); in gk20a_pmu_dvfs_get_target_state()
100 status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
101 status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
109 nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
110 nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
125 u32 utilization = 0; in gk20a_pmu_dvfs_work()
161 nvkm_timer_alarm(pmu->subdev.device->timer, 0, &gpmu->alarm); in gk20a_pmu_fini()
182 nvkm_falcon_wr32(falcon, 0x504 + (BUSY_SLOT * 0x10), 0x00200001); in gk20a_pmu_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/usb/au0828/ |
| D | au0828-reg.h | 11 #define REG_000 0x000
12 #define REG_001 0x001
13 #define REG_002 0x002
14 #define REG_003 0x003
16 #define AU0828_SENSORCTRL_100 0x100
17 #define AU0828_SENSORCTRL_VBI_103 0x103
20 #define AU0828_I2C_TRIGGER_200 0x200
21 #define AU0828_I2C_STATUS_201 0x201
22 #define AU0828_I2C_CLK_DIVIDER_202 0x202
23 #define AU0828_I2C_DEST_ADDR_203 0x203
[all …]
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| /kernel/linux/linux-5.10/drivers/media/usb/au0828/ |
| D | au0828-reg.h | 11 #define REG_000 0x000
12 #define REG_001 0x001
13 #define REG_002 0x002
14 #define REG_003 0x003
16 #define AU0828_SENSORCTRL_100 0x100
17 #define AU0828_SENSORCTRL_VBI_103 0x103
20 #define AU0828_I2C_TRIGGER_200 0x200
21 #define AU0828_I2C_STATUS_201 0x201
22 #define AU0828_I2C_CLK_DIVIDER_202 0x202
23 #define AU0828_I2C_DEST_ADDR_203 0x203
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_mst_types.h | 29 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C
33 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case
36 #define IS_SYNAPTICS_PANAMERA(branchDevName) (((int)branchDevName[4] & 0xF0) == 0x50 ? 1 : 0)
37 #define BRANCH_HW_REVISION_PANAMERA_A2 0x10
38 #define SYNAPTICS_CASCADED_HUB_ID 0x5A
39 …me, data) ((IS_SYNAPTICS_PANAMERA(devName) && ((int)data[2] == SYNAPTICS_CASCADED_HUB_ID)) ? 1 : 0)
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/ |
| D | sun4i_hdmi.h | 17 #define SUN4I_HDMI_CTRL_REG 0x004
20 #define SUN4I_HDMI_IRQ_REG 0x008
21 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
23 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
25 #define SUN4I_HDMI_HPD_REG 0x00c
26 #define SUN4I_HDMI_HPD_HIGH BIT(0)
28 #define SUN4I_HDMI_VID_CTRL_REG 0x010
32 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
33 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
34 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/ |
| D | sun4i_hdmi.h | 17 #define SUN4I_HDMI_CTRL_REG 0x004
20 #define SUN4I_HDMI_IRQ_REG 0x008
21 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
23 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
25 #define SUN4I_HDMI_HPD_REG 0x00c
26 #define SUN4I_HDMI_HPD_HIGH BIT(0)
28 #define SUN4I_HDMI_VID_CTRL_REG 0x010
32 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
33 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
34 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/ |
| D | odm_reg.h | 16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
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| D | odm_RegDefine11N.h | 13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/ |
| D | odm_reg.h | 16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_mst_types.h | 29 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
31 #define SYNAPTICS_RC_COMMAND 0x4B2
32 #define SYNAPTICS_RC_RESULT 0x4B3
33 #define SYNAPTICS_RC_LENGTH 0x4B8
34 #define SYNAPTICS_RC_OFFSET 0x4BC
35 #define SYNAPTICS_RC_DATA 0x4C0
37 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C
41 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case
44 #define IS_SYNAPTICS_PANAMERA(branchDevName) (((int)branchDevName[4] & 0xF0) == 0x50 ? 1 : 0)
45 #define BRANCH_HW_REVISION_PANAMERA_A2 0x10
[all …]
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| /kernel/linux/linux-5.10/drivers/media/usb/stk1160/ |
| D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
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| /kernel/linux/linux-6.6/drivers/media/usb/stk1160/ |
| D | stk1160-reg.h | 14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8188eu/hal/ |
| D | mac_cfg.c | 14 0x026, 0x00000041,
15 0x027, 0x00000035,
16 0x428, 0x0000000A,
17 0x429, 0x00000010,
18 0x430, 0x00000000,
19 0x431, 0x00000001,
20 0x432, 0x00000002,
21 0x433, 0x00000004,
22 0x434, 0x00000005,
23 0x435, 0x00000006,
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
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