Searched +full:0 +full:x61c (Results 1 – 25 of 70) sorted by relevance
123
71 reg = <0x400e8000 0x4000>;74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
26 #define CG_SPLL_FUNC_CNTL 0x60027 #define SPLL_RESET (1 << 0)31 #define SPLL_REF_DIV_MASK (0x3f << 4)33 #define SPLL_PDIV_A_MASK (0x7f << 20)34 #define CG_SPLL_FUNC_CNTL_2 0x60435 #define SCLK_MUX_SEL(x) ((x) << 0)36 #define SCLK_MUX_SEL_MASK (0x1ff << 0)37 #define CG_SPLL_FUNC_CNTL_3 0x60838 #define SPLL_FB_DIV(x) ((x) << 0)39 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)[all …]
30 #define RCU_FW_VERSION 0x30c32 #define RCU_PWR_GATING_SEQ0 0x40833 #define RCU_PWR_GATING_SEQ1 0x40c34 #define RCU_PWR_GATING_CNTL 0x41035 # define PWR_GATING_EN (1 << 0)36 # define RSVD_MASK (0x3 << 1)38 # define PCV_MASK (0x1f << 3)41 # define PCP_MASK (0xf << 8)44 # define RPW_MASK (0xf << 16)47 # define ID_MASK (0xf << 24)[all …]
13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x014 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x015 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x016 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x017 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x018 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x019 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x020 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x021 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x022 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0[all …]
13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x014 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x015 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x016 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x017 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x018 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x019 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x020 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x021 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x022 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0[all …]
13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x014 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x015 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x016 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x017 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x018 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x019 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x020 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x021 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x022 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0[all …]
13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x014 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x015 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x016 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x017 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x018 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x019 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x020 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x021 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x022 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0[all …]
13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x014 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x015 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x016 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x017 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x018 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x019 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x020 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x021 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x022 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0[all …]
15 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)17 #define WIN_FEATURE_AFBDC BIT(0)198 #define RK3568_GRF_VO_CON1 0x0364200 #define RK3568_REG_CFG_DONE 0x000201 #define RK3568_VERSION_INFO 0x004202 #define RK3568_SYS_AUTO_GATING_CTRL 0x008203 #define RK3568_SYS_AXI_LUT_CTRL 0x024204 #define RK3568_DSP_IF_EN 0x028205 #define RK3568_DSP_IF_CTRL 0x02c206 #define RK3568_DSP_IF_POL 0x030[all …]
11 #define VIDCON0 0x0016 #define VIDCON0_ENVID_F (1 << 0)19 #define VIDOUTCON0 0x421 #define VIDOUTCON0_DUAL_MASK (0x3 << 24)22 #define VIDOUTCON0_DUAL_ON (0x3 << 24)23 #define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)24 #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)25 #define VIDOUTCON0_DUAL_OFF (0x0 << 24)27 #define VIDOUTCON0_IF_MASK (0x1 << 23)28 #define VIDOUTCON0_RGBIF (0x0 << 23)[all …]
10 #define MT6331_STRUP_CON0 0x011 #define MT6331_STRUP_CON2 0x212 #define MT6331_STRUP_CON3 0x413 #define MT6331_STRUP_CON4 0x614 #define MT6331_STRUP_CON5 0x815 #define MT6331_STRUP_CON6 0xA16 #define MT6331_STRUP_CON7 0xC17 #define MT6331_STRUP_CON8 0xE18 #define MT6331_STRUP_CON9 0x1019 #define MT6331_STRUP_CON10 0x12[all …]
32 * [5:0]: Number of NOPs or registers to set values to in case of37 * is used for offsets smaller than 0x200 while the latter is for values bigger42 * [6:0]: Register offset, without considering the engine base.53 #define POSTED BIT(0) in set_offsets()54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()56 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()57 (((x) >> 2) & 0x7f) in set_offsets()58 #define END 0 in set_offsets()71 count = *data & 0x3f; in set_offsets()84 u32 offset = 0; in set_offsets()[all …]
8 #define MT_MCU_WFDMA1_BASE 0x300011 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)17 #define MT_PLE_BASE 0x800020 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)25 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \27 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))[all …]
19 #define DESC_ADDR_HI_STATUS_LEN 0x0020 #define DESC_ADDR_HI_SHIFT 021 #define DESC_ADDR_HI_MASK 0xff23 #define DESC_STATUS_MASK 0x3ff25 #define DESC_LEN_MASK 0x7fff26 #define DESC_ADDR_LO 0x0445 #define PCP_DEI_MASK 0xf47 #define VID_MASK 0xfff49 #define L4_CSUM_PTR_MASK 0x1ff51 #define L4_PTR_MASK 0x1ff[all …]
31 #define CCR 0x032 #define BM_CCR_WB_COUNT (0x7 << 16)33 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)34 #define BM_CCR_RBC_EN (0x1 << 27)36 #define CLPCR 0x5437 #define BP_CLPCR_LPM 038 #define BM_CLPCR_LPM (0x3 << 0)39 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)40 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)41 #define BM_CLPCR_SBYOS (0x1 << 6)[all …]
29 #define CCR 0x030 #define BM_CCR_WB_COUNT (0x7 << 16)31 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)32 #define BM_CCR_RBC_EN (0x1 << 27)34 #define CLPCR 0x5435 #define BP_CLPCR_LPM 036 #define BM_CLPCR_LPM (0x3 << 0)37 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)38 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)39 #define BM_CLPCR_SBYOS (0x1 << 6)[all …]
34 #define DMA_MAX_BURST_LENGTH 0x1038 #define CLEAR_ALL_HFB 0xFF53 #define STATUS_RX_EXT_MASK 0x1FFFFF54 #define STATUS_RX_CSUM_MASK 0xFFFF55 #define STATUS_RX_CSUM_OK 0x1000056 #define STATUS_RX_CSUM_FR 0x2000057 #define STATUS_RX_PROTO_TCP 063 #define STATUS_FILTER_INDEX_MASK 0xFFFF65 #define STATUS_TX_CSUM_START_MASK 0X7FFF67 #define STATUS_TX_CSUM_PROTO_UDP 0x8000[all …]