Home
last modified time | relevance | path

Searched +full:0 +full:x620 (Results 1 – 25 of 230) sorted by relevance

12345678910

/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dacadia.dts18 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
34 clock-frequency = <0>; /* Filled in by wrapper */
35 timebase-frequency = <0>; /* Filled in by wrapper */
47 reg = <0x0 0x0>; /* Filled in by wrapper */
53 dcr-reg = <0x0c0 0x009>;
54 cell-index = <0>;
55 #address-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dacadia.dts18 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
34 clock-frequency = <0>; /* Filled in by wrapper */
35 timebase-frequency = <0>; /* Filled in by wrapper */
47 reg = <0x0 0x0>; /* Filled in by wrapper */
53 dcr-reg = <0x0c0 0x009>;
54 cell-index = <0>;
55 #address-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7785.c27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
33 .id = 0,
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
111 DEFINE_RES_MEM(0xffee0000, 0x100),
[all …]
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7785.c27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
33 .id = 0,
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
111 DEFINE_RES_MEM(0xffee0000, 0x100),
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-se/mach/
Dse7724.h21 #define SH_ETH_ADDR (0xA4600000)
22 #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
23 #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
25 #define PA_LED (0xba203000) /* 8bit LED */
26 #define IRQ_MODE (0xba200010)
27 #define IRQ0_SR (0xba200014)
28 #define IRQ1_SR (0xba200018)
29 #define IRQ2_SR (0xba20001c)
30 #define IRQ0_MR (0xba200020)
31 #define IRQ1_MR (0xba200024)
[all …]
Dse7722.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
23 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE 0x04000000
26 #define PA_EXT4 0xb0000000
27 #define PA_EXT4_SIZE 0x04000000
[all …]
Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
/kernel/linux/linux-6.6/arch/sh/include/mach-se/mach/
Dse7724.h21 #define SH_ETH_ADDR (0xA4600000)
22 #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
23 #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
25 #define PA_LED (0xba203000) /* 8bit LED */
26 #define IRQ_MODE (0xba200010)
27 #define IRQ0_SR (0xba200014)
28 #define IRQ1_SR (0xba200018)
29 #define IRQ2_SR (0xba20001c)
30 #define IRQ0_MR (0xba200020)
31 #define IRQ1_MR (0xba200024)
[all …]
Dse7722.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
23 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE 0x04000000
26 #define PA_EXT4 0xb0000000
27 #define PA_EXT4_SIZE 0x04000000
[all …]
Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh3/
Dsetup-sh3.c16 UNUSED = 0,
23 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
24 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
28 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
32 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
33 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
37 { 0xa4000004, 0, 8, /* IRR0 */
38 { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
42 { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
53 #define INTC_ICR1 0xa4000010UL
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh3/
Dsetup-sh3.c16 UNUSED = 0,
23 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
24 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
28 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
32 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
33 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
37 { 0xa4000004, 0, 8, /* IRR0 */
38 { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
42 { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
53 #define INTC_ICR1 0xa4000010UL
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dfsl,imxrt1170.yaml71 reg = <0x400e8000 0x4000>;
74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
/kernel/linux/linux-6.6/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-6.6/arch/alpha/include/asm/
Derr_common.h17 #define SCB_Q_SYSERR 0x620
18 #define SCB_Q_PROCERR 0x630
19 #define SCB_Q_SYSMCHK 0x660
20 #define SCB_Q_PROCMCHK 0x670
21 #define SCB_Q_SYSEVENT 0x680
26 #define MCHK_DISPOSITION_UNKNOWN_ERROR 0x00
27 #define MCHK_DISPOSITION_REPORT 0x01
28 #define MCHK_DISPOSITION_DISMISS 0x02
37 #define EL_CLASS__TERMINATION (0)
38 # define EL_TYPE__TERMINATION__TERMINATION (0)
/kernel/linux/linux-5.10/arch/alpha/include/asm/
Derr_common.h17 #define SCB_Q_SYSERR 0x620
18 #define SCB_Q_PROCERR 0x630
19 #define SCB_Q_SYSMCHK 0x660
20 #define SCB_Q_PROCMCHK 0x670
21 #define SCB_Q_SYSEVENT 0x680
26 #define MCHK_DISPOSITION_UNKNOWN_ERROR 0x00
27 #define MCHK_DISPOSITION_REPORT 0x01
28 #define MCHK_DISPOSITION_DISMISS 0x02
37 #define EL_CLASS__TERMINATION (0)
38 # define EL_TYPE__TERMINATION__TERMINATION (0)
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dusb.h8 #define CONF2_NO_OVERRIDE (0 << 14)
17 #define CONF2_REFFREQ (0xf << 8)
27 #define USBCTRL0 0x620
28 #define USBSTAT0 0x624
31 #define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
35 #define USBPHY_CM_PWRDN (1 << 0)
61 bool vcc_polarity; /* 1 active high, 0 active low */
/kernel/linux/linux-5.10/drivers/platform/x86/
Dintel-uncore-frequency.c24 #define MSR_UNCORE_RATIO_LIMIT 0x620
94 /* Common function to read MSR 0x620 and read min/max */
101 if (data->control_cpu < 0) in uncore_read_ratio()
108 *max = (cap & 0x7F) * UNCORE_FREQ_KHZ_MULTIPLIER; in uncore_read_ratio()
111 return 0; in uncore_read_ratio()
123 if (data->control_cpu < 0) { in uncore_write_ratio()
129 if (!input || input > 0x7F) { in uncore_write_ratio()
139 cap &= ~0x7F; in uncore_write_ratio()
212 store_uncore_min_max(min_freq_khz, 0);
215 show_uncore_min_max(min_freq_khz, 0);
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddra72x-mmc-iodelay.dtsi45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
49 return rc < 0 ? rc : 0; in lan88xx_phy_config_intr()
56 return rc < 0 ? rc : 0; in lan88xx_phy_ack_interrupt()
67 return 0; in lan88xx_suspend()
73 int val, save_page, ret = 0; in lan88xx_TR_reg_set()
78 if (save_page < 0) { in lan88xx_TR_reg_set()
87 (data & 0xFFFF)); in lan88xx_TR_reg_set()
88 if (ret < 0) { in lan88xx_TR_reg_set()
94 (data & 0x00FF0000) >> 16); in lan88xx_TR_reg_set()
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dmicrochip.c42 return 0; in lan88xx_suspend()
48 int val, save_page, ret = 0; in lan88xx_TR_reg_set()
53 if (save_page < 0) { in lan88xx_TR_reg_set()
62 (data & 0xFFFF)); in lan88xx_TR_reg_set()
63 if (ret < 0) { in lan88xx_TR_reg_set()
69 (data & 0x00FF0000) >> 16); in lan88xx_TR_reg_set()
70 if (ret < 0) { in lan88xx_TR_reg_set()
76 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */ in lan88xx_TR_reg_set()
77 buf |= 0x8000; /* Set [15] to Packet transmit */ in lan88xx_TR_reg_set()
80 if (ret < 0) { in lan88xx_TR_reg_set()
[all …]

12345678910