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/kernel/linux/linux-5.10/drivers/misc/habanalabs/gaudi/
Dgaudi_security.c481 while (pb_addr & 0xFFF) { in gaudi_pb_set_block()
482 WREG32(pb_addr, 0); in gaudi_pb_set_block()
505 WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
506 WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
507 WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
508 WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
510 WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
511 WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
513 pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_mme_protection_bits()
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/gaudi/
Dgaudi_security.c481 while (pb_addr & 0xFFF) { in gaudi_pb_set_block()
482 WREG32(pb_addr, 0); in gaudi_pb_set_block()
505 WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
506 WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
507 WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
508 WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
510 WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
511 WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); in gaudi_init_mme_protection_bits()
513 pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_mme_protection_bits()
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/goya/
Dgoya_security.c22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/goya/
Dgoya_security.c22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv50.c32 /* 0x01: no bank swizzle in nv50_mmu_kind()
33 * 0x02: bank swizzled in nv50_mmu_kind()
34 * 0x7f: invalid in nv50_mmu_kind()
36 * 0x01/0x02 are values understood by the VRAM allocator, in nv50_mmu_kind()
42 0x01, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x00 */ in nv50_mmu_kind()
43 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
44 0x01, 0x01, 0x01, 0x01, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x10 */ in nv50_mmu_kind()
45 0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
46 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x20 */ in nv50_mmu_kind()
47 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f, in nv50_mmu_kind()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv50.c32 /* 0x01: no bank swizzle in nv50_mmu_kind()
33 * 0x02: bank swizzled in nv50_mmu_kind()
34 * 0x7f: invalid in nv50_mmu_kind()
36 * 0x01/0x02 are values understood by the VRAM allocator, in nv50_mmu_kind()
42 0x01, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x00 */ in nv50_mmu_kind()
43 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
44 0x01, 0x01, 0x01, 0x01, 0x7f, 0x7f, 0x7f, 0x7f, /* 0x10 */ in nv50_mmu_kind()
45 0x02, 0x02, 0x02, 0x02, 0x7f, 0x7f, 0x7f, 0x7f, in nv50_mmu_kind()
46 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, /* 0x20 */ in nv50_mmu_kind()
47 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7f, in nv50_mmu_kind()
[all …]
/kernel/linux/linux-6.6/drivers/regulator/
Drn5t618-regulator.c45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
56 REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1200000, 3500000, 25000),
[all …]
Dmt6358-regulator.c16 #define MT6358_BUCK_MODE_AUTO 0
56 .enable_mask = BIT(0), \
60 .qi = BIT(0), \
108 .enable_mask = BIT(0), \
113 .qi = BIT(0), \
152 .enable_mask = BIT(0), \
156 .qi = BIT(0), \
204 .enable_mask = BIT(0), \
209 .qi = BIT(0), \
280 0, 12,
[all …]
Drc5t583-regulator.c83 RC5T583_REG(DC0, DC0CTL, 0, DC0CTL, 1, 0x7F, 700, 1500, 12500, 4),
84 RC5T583_REG(DC1, DC1CTL, 0, DC1CTL, 1, 0x7F, 700, 1500, 12500, 14),
85 RC5T583_REG(DC2, DC2CTL, 0, DC2CTL, 1, 0x7F, 900, 2400, 12500, 14),
86 RC5T583_REG(DC3, DC3CTL, 0, DC3CTL, 1, 0x7F, 900, 2400, 12500, 14),
87 RC5T583_REG(LDO0, LDOEN2, 0, LDODIS2, 0, 0x7F, 900, 3400, 25000, 160),
88 RC5T583_REG(LDO1, LDOEN2, 1, LDODIS2, 1, 0x7F, 900, 3400, 25000, 160),
89 RC5T583_REG(LDO2, LDOEN2, 2, LDODIS2, 2, 0x7F, 900, 3400, 25000, 160),
90 RC5T583_REG(LDO3, LDOEN2, 3, LDODIS2, 3, 0x7F, 900, 3400, 25000, 160),
91 RC5T583_REG(LDO4, LDOEN2, 4, LDODIS2, 4, 0x3F, 750, 1500, 12500, 133),
92 RC5T583_REG(LDO5, LDOEN2, 5, LDODIS2, 5, 0x7F, 900, 3400, 25000, 267),
[all …]
/kernel/linux/linux-5.10/drivers/regulator/
Drn5t618-regulator.c45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
56 REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1200000, 3500000, 25000),
[all …]
Dmt6358-regulator.c16 #define MT6358_BUCK_MODE_AUTO 0
57 .enable_mask = BIT(0), \
61 .qi = BIT(0), \
112 .enable_mask = BIT(0), \
118 .qi = BIT(0), \
141 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
145 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
149 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
153 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
204 0, 12,
[all …]
Drc5t583-regulator.c84 RC5T583_REG(DC0, DC0CTL, 0, DC0CTL, 1, 0x7F, 700, 1500, 12500, 4),
85 RC5T583_REG(DC1, DC1CTL, 0, DC1CTL, 1, 0x7F, 700, 1500, 12500, 14),
86 RC5T583_REG(DC2, DC2CTL, 0, DC2CTL, 1, 0x7F, 900, 2400, 12500, 14),
87 RC5T583_REG(DC3, DC3CTL, 0, DC3CTL, 1, 0x7F, 900, 2400, 12500, 14),
88 RC5T583_REG(LDO0, LDOEN2, 0, LDODIS2, 0, 0x7F, 900, 3400, 25000, 160),
89 RC5T583_REG(LDO1, LDOEN2, 1, LDODIS2, 1, 0x7F, 900, 3400, 25000, 160),
90 RC5T583_REG(LDO2, LDOEN2, 2, LDODIS2, 2, 0x7F, 900, 3400, 25000, 160),
91 RC5T583_REG(LDO3, LDOEN2, 3, LDODIS2, 3, 0x7F, 900, 3400, 25000, 160),
92 RC5T583_REG(LDO4, LDOEN2, 4, LDODIS2, 4, 0x3F, 750, 1500, 12500, 133),
93 RC5T583_REG(LDO5, LDOEN2, 5, LDODIS2, 5, 0x7F, 900, 3400, 25000, 267),
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/verisilicon/
Drockchip_vpu981_regs.h28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
39 #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1)
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/mt6359/
Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/kernel/linux/linux-5.10/drivers/staging/vt6656/
Drf.c36 {0x03, 0xf7, 0x90},
37 {0x03, 0x33, 0x31},
38 {0x01, 0xb8, 0x02},
39 {0x00, 0xff, 0xf3},
40 {0x00, 0x05, 0xa4},
41 {0x0f, 0x4d, 0xc5},
42 {0x08, 0x05, 0xb6},
43 {0x01, 0x47, 0xc7},
44 {0x00, 0x06, 0x88},
45 {0x04, 0x03, 0xb9},
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x0/
Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt76x0/
Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/kernel/linux/linux-6.6/include/linux/regulator/
Dpca9450.h10 PCA9450_TYPE_PCA9450A = 0,
16 PCA9450_BUCK1 = 0,
31 PCA9450_DVS_LEVEL_RUN = 0,
36 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
37 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
38 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
41 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
42 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
44 #define PCA9450_LDO1_VOLTAGE_NUM 0x08
[all …]
/kernel/linux/linux-5.10/include/linux/regulator/
Dpca9450.h10 PCA9450_TYPE_PCA9450A = 0,
16 PCA9450_BUCK1 = 0,
31 PCA9450_DVS_LEVEL_RUN = 0,
36 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
37 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
38 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
41 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
42 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
44 #define PCA9450_LDO1_VOLTAGE_NUM 0x08
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_ddi_buf_trans.c19 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
20 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
21 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
22 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
23 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
24 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
25 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
26 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
27 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
36 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Drtl2832_priv.h242 {DVBT_DAGC_TRG_VAL, 0x39},
243 {DVBT_AGC_TARG_VAL_0, 0x0},
244 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
245 {DVBT_AAGC_LOOP_GAIN, 0x16},
246 {DVBT_LOOP_GAIN2_3_0, 0x6},
247 {DVBT_LOOP_GAIN2_4, 0x1},
248 {DVBT_LOOP_GAIN3, 0x16},
249 {DVBT_VTOP1, 0x35},
250 {DVBT_VTOP2, 0x21},
251 {DVBT_VTOP3, 0x21},
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Drtl2832_priv.h242 {DVBT_DAGC_TRG_VAL, 0x39},
243 {DVBT_AGC_TARG_VAL_0, 0x0},
244 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
245 {DVBT_AAGC_LOOP_GAIN, 0x16},
246 {DVBT_LOOP_GAIN2_3_0, 0x6},
247 {DVBT_LOOP_GAIN2_4, 0x1},
248 {DVBT_LOOP_GAIN3, 0x16},
249 {DVBT_VTOP1, 0x35},
250 {DVBT_VTOP2, 0x21},
251 {DVBT_VTOP3, 0x21},
[all …]
/kernel/linux/linux-5.10/lib/fonts/
Dfont_ter16x32.c8 { 0, 0, FONTDATAMAX, 0 }, {
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 0x7f, 0xfc,
11 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
12 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
13 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
14 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
15 0x7f, 0xfc, 0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/kernel/linux/linux-6.6/lib/fonts/
Dfont_ter16x32.c8 { 0, 0, FONTDATAMAX, 0 }, {
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 0x7f, 0xfc,
11 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
12 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
13 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
14 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
15 0x7f, 0xfc, 0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/kernel/linux/linux-6.6/sound/core/seq/
Dseq_ump_convert.c37 if (src <= 0x40) in upscale_7_to_16bit()
39 repeat = src & 0x3f; in upscale_7_to_16bit()
48 if (src <= 0x40) in upscale_7_to_32bit()
50 repeat = src & 0x3f; in upscale_7_to_32bit()
60 if (src <= 0x2000) in upscale_14_to_32bit()
62 repeat = src & 0x1fff; in upscale_14_to_32bit()
68 return port->ump_group ? (port->ump_group - 1) : 0; in get_ump_group()
73 ump_compose(type, get_ump_group(port), 0, 0)
122 /* Encoders for MIDI1 status 0x80-0xe0 */
124 {SNDRV_SEQ_EVENT_NOTEOFF, ump_midi1_to_note_ev}, /* 0x80 */
[all …]

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