Home
last modified time | relevance | path

Searched +full:0 +full:xb00 (Results 1 – 25 of 275) sorted by relevance

1234567891011

/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
Dkeystone-k2e-clocks.dtsi10 #clock-cells = <0>;
13 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
18 #clock-cells = <0>;
22 reg = <0x02620358 4>;
27 #clock-cells = <0>;
31 reg = <0x02620360 4>;
36 #clock-cells = <0>;
40 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
42 domain-id = <0>;
46 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
Dkeystone-k2e-clocks.dtsi10 #clock-cells = <0>;
13 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
18 #clock-cells = <0>;
22 reg = <0x02620358 4>;
27 #clock-cells = <0>;
31 reg = <0x02620360 4>;
36 #clock-cells = <0>;
40 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
42 domain-id = <0>;
46 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/mediatek/
Dpinctrl-mt8127.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
Dpinctrl-mt6795.c11 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
12 _x_bits, 15, 0)
15 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 16, 0)
19 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
23 PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
27 PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
31 PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
35 PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
39 PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt8127.c20 /* 0E4E8SR 4/8/12/16 */
22 /* 0E2E4SR 2/4/6/8 */
25 MTK_DRV_GRP(2, 16, 0, 2, 2)
29 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
35 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-audio.c15 #define CX18_AUDIO_ENABLE 0xc72014
16 #define CX18_AI1_MUX_MASK 0x30
17 #define CX18_AI1_MUX_I2S1 0x00
18 #define CX18_AI1_MUX_I2S2 0x10
19 #define CX18_AI1_MUX_843_I2S 0x20
37 (u32) in->muxer_input, 0, 0); in cx18_audio_set_io()
40 audio, s_routing, in->audio_input, 0, 0); in cx18_audio_set_io()
72 cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE, in cx18_audio_set_io()
75 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_audio_set_io()
77 return 0; in cx18_audio_set_io()
Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/kernel/linux/linux-6.6/drivers/media/pci/cx18/
Dcx18-audio.c15 #define CX18_AUDIO_ENABLE 0xc72014
16 #define CX18_AI1_MUX_MASK 0x30
17 #define CX18_AI1_MUX_I2S1 0x00
18 #define CX18_AI1_MUX_I2S2 0x10
19 #define CX18_AI1_MUX_843_I2S 0x20
37 (u32) in->muxer_input, 0, 0); in cx18_audio_set_io()
40 audio, s_routing, in->audio_input, 0, 0); in cx18_audio_set_io()
72 cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE, in cx18_audio_set_io()
75 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_audio_set_io()
77 return 0; in cx18_audio_set_io()
Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
Dhal_phy_reg_8723b.h14 /* 4. Page9(0x900) */
16 #define rDPDT_control 0x92c
17 #define rfe_ctrl_anta_src 0x930
18 #define rS0S1_PathSwitch 0x948
19 #define AGC_table_select 0xb2c
22 /* PageB(0xB00) */
24 #define rPdp_AntA 0xb00
25 #define rPdp_AntA_4 0xb04
26 #define rPdp_AntA_8 0xb08
27 #define rPdp_AntA_C 0xb0c
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
Dhal_phy_reg_8723b.h14 /* 4. Page9(0x900) */
16 #define rDPDT_control 0x92c
17 #define rfe_ctrl_anta_src 0x930
18 #define rS0S1_PathSwitch 0x948
19 #define AGC_table_select 0xb2c
22 /* PageB(0xB00) */
24 #define rPdp_AntA 0xb00
25 #define rPdp_AntA_4 0xb04
26 #define rPdp_AntA_8 0xb08
27 #define rPdp_AntA_C 0xb0c
[all …]
/kernel/linux/linux-6.6/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-mt7621.txt7 - #size-cells: should be 0.
21 reg = <0xb00 0x100>;
23 #size-cells = <0>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dkeystone-gate.txt11 - #clock-cells : from common clock binding; shall be set to 0.
22 #clock-cells = <0>;
26 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
28 domain-id = <0>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dkeystone-gate.txt11 - #clock-cells : from common clock binding; shall be set to 0.
22 #clock-cells = <0>;
26 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
28 domain-id = <0>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dralink,mt7621-spi.yaml50 reg = <0xb00 0x100>;
57 #size-cells = <0>;
60 pinctrl-0 = <&spi_pins>;
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]

1234567891011