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/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
46 - const: sifive,plic-1.0.0
52 const: 0
85 #address-cells = <0>;
87 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
95 reg = <0xc000000 0x4000000>;
/kernel/linux/linux-5.10/arch/riscv/boot/dts/kendryte/
Dk210.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0>;
37 i-cache-size = <0x8000>;
39 d-cache-size = <0x8000>;
55 i-cache-size = <0x8000>;
57 d-cache-size = <0x8000>;
71 reg = <0x80000000 0x400000>,
72 <0x80400000 0x200000>,
73 <0x80600000 0x200000>;
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
39 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
40 * 3. RF register 0x00-2E
45 * 1. Page1(0x100)
47 #define rPMAC_Reset 0x100
48 #define rPMAC_TxStart 0x104
49 #define rPMAC_TxLegacySIG 0x108
50 #define rPMAC_TxHTSIG1 0x10c
51 #define rPMAC_TxHTSIG2 0x110
52 #define rPMAC_PHYDebug 0x114
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39 * 3. RF register 0x00-2E
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
47 #define rPMAC_TxStart 0x104
48 #define rPMAC_TxLegacySIG 0x108
49 #define rPMAC_TxHTSIG1 0x10c
50 #define rPMAC_TxHTSIG2 0x110
51 #define rPMAC_PHYDebug 0x114
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
64 - const: sifive,plic-1.0.0
71 - const: sifive,plic-1.0.0
80 const: 0
160 #address-cells = <0>;
162 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
169 reg = <0xc000000 0x4000000>;
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ralink/
Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/ralink/
Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dat91sam9m10g45ek.dts22 reg = <0x70000000 0x4000000>;
42 timer@0 {
44 reg = <0>, <1>;
54 pinctrl-0 =
70 reg = <0x30>;
72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
98 pinctrl-0 = <
104 slot@0 {
105 reg = <0>;
112 pinctrl-0 = <
[all …]
/kernel/linux/linux-6.6/sound/soc/fsl/
Dfsl_xcvr.h11 #define FSL_XCVR_MODE_SPDIF 0
16 #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */
17 #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */
23 #define FSL_XCVR_RX_FIFO_ADDR 0x0C00
24 #define FSL_XCVR_TX_FIFO_ADDR 0x0E00
26 #define FSL_XCVR_VERSION 0x00 /* Version */
27 #define FSL_XCVR_EXT_CTRL 0x10 /* Control */
28 #define FSL_XCVR_EXT_STATUS 0x20 /* Status */
29 #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */
30 #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7100.dtsi18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
110 #clock-cells = <0>;
112 clock-frequency = <0>;
117 #clock-cells = <0>;
119 clock-frequency = <0>;
124 #clock-cells = <0>;
126 clock-frequency = <0>;
131 #clock-cells = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath11k.yaml161 reg = <0xCD00000 0x4040>,
162 <0x4AB000 0x20>;
169 reg = <0xc000000 0x2000000>;
170 interrupts = <0 320 1>,
171 <0 319 1>,
172 <0 318 1>,
173 <0 317 1>,
174 <0 316 1>,
175 <0 315 1>,
176 <0 314 1>,
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dat91sam9m10g45ek.dts22 reg = <0x70000000 0x4000000>;
42 timer@0 {
44 reg = <0>, <1>;
54 pinctrl-0 =
70 reg = <0x30>;
72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
98 pinctrl-0 = <
104 slot@0 {
105 reg = <0>;
112 pinctrl-0 = <
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]

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