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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml106 "^dwc3@[0-9a-f]+$":
137 reg = <0 0x0a6f8800 0 0x400>;
167 reg = <0 0x0a600000 0 0xcd00>;
169 iommus = <&apps_smmu 0x740 0>;
/kernel/linux/linux-5.10/drivers/staging/media/meson/vdec/
Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/meson/vdec/
Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dipq8074.dtsi17 #clock-cells = <0>;
23 #clock-cells = <0>;
28 #address-cells = <0x1>;
29 #size-cells = <0x0>;
31 CPU0: cpu@0 {
34 reg = <0x0>;
43 reg = <0x1>;
51 reg = <0x2>;
59 reg = <0x3>;
65 cache-level = <0x2>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
79 #size-cells = <0>;
[all …]
Duniphier-pro5.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
[all …]
Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
162 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
163 <0x506c0000 0x400>;
164 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
175 reg = <0x54006000 0x100>;
177 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/socionext/
Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml117 "^usb@[0-9a-f]+$":
495 reg = <0 0x0a6f8800 0 0x400>;
528 reg = <0 0x0a600000 0 0xcd00>;
530 iommus = <&apps_smmu 0x740 0>;
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dipq6018.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
64 reg = <0x2>;
76 reg = <0x3>;
94 qcom,dload-mode = <&tcsr 0x6100>;
156 mboxes = <&apcs_glb 0>;
[all …]
Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
Dipq9574.dtsi23 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
65 reg = <0x2>;
78 reg = <0x3>;
98 qcom,dload-mode = <&tcsr 0x6100>;
105 reg = <0x0 0x40000000 0x0 0x0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi20 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0 0x000>;
52 reg = <0 0x001>;
62 reg = <0 0x002>;
72 reg = <0 0x003>;
126 #clock-cells = <0>;
181 reg = <0x0 0x81000000 0x0 0x01000000>;
186 soc@0 {
190 ranges = <0 0 0 0xffffffff>;
[all …]
Duniphier-ld20.dtsi20 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0 0x000>;
55 reg = <0 0x001>;
65 reg = <0 0x100>;
75 reg = <0 0x101>;
167 #clock-cells = <0>;
222 reg = <0x0 0x81000000 0x0 0x01000000>;
227 soc@0 {
231 ranges = <0 0 0 0xffffffff>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
/kernel/linux/linux-5.10/drivers/ptp/
Didt8a340_reg.h8 * Based on 4.8.0, SCSR rev C commit a03c7ae5
13 #define PAGE_ADDR_BASE 0x0000
14 #define PAGE_ADDR 0x00fc
16 #define HW_REVISION 0x8180
17 #define REV_ID 0x007a
19 #define HW_DPLL_0 (0x8a00)
20 #define HW_DPLL_1 (0x8b00)
21 #define HW_DPLL_2 (0x8c00)
22 #define HW_DPLL_3 (0x8d00)
23 #define HW_DPLL_4 (0x8e00)
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dqcom-ipq8064.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
[all …]
Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Didt8a340_reg.h3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Drt1318-sdw.c24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x33 },
29 { 0xc007, 0x64 },
30 { 0xc320, 0x20 },
31 { 0xf203, 0x18 },
32 { 0xf211, 0x00 },
33 { 0xf212, 0x26 },
[all …]
/kernel/linux/linux-5.10/drivers/usb/dwc3/
Ddwc3-qcom.c27 #define QSCRATCH_HS_PHY_CTRL 0x10
31 #define QSCRATCH_SS_PHY_CTRL 0x30
34 #define QSCRATCH_GENERAL_CFG 0x08
35 #define PIPE_UTMI_CLK_SEL BIT(0)
39 #define PWR_EVNT_IRQ_STAT_REG 0x58
43 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44 #define SDM845_QSCRATCH_SIZE 0x400
45 #define SDM845_DWC3_CORE_SIZE 0xcd00
52 #define APPS_USB_AVG_BW 0
164 return 0; in dwc3_qcom_register_extcon()
[all …]
/kernel/linux/linux-6.6/drivers/usb/dwc3/
Ddwc3-qcom.c28 #define QSCRATCH_HS_PHY_CTRL 0x10
32 #define QSCRATCH_SS_PHY_CTRL 0x30
35 #define QSCRATCH_GENERAL_CFG 0x08
36 #define PIPE_UTMI_CLK_SEL BIT(0)
40 #define PWR_EVNT_IRQ_STAT_REG 0x58
44 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
45 #define SDM845_QSCRATCH_SIZE 0x400
46 #define SDM845_DWC3_CORE_SIZE 0xcd00
53 #define APPS_USB_AVG_BW 0
166 return 0; in dwc3_qcom_register_extcon()
[all …]

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