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/kernel/linux/linux-6.6/drivers/pinctrl/mediatek/
Dpinctrl-mt8167.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8516.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8127.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
Dpinctrl-mt2701.c38 /* 0E4E8SR 4/8/12/16 */
40 /* 0E2E4SR 2/4/6/8 */
43 MTK_DRV_GRP(2, 16, 0, 2, 2)
47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
Dpinctrl-mt7623.c13 #define PIN_BOND_REG0 0xb10
14 #define PIN_BOND_REG1 0xf20
15 #define PIN_BOND_REG2 0xef0
16 #define BOND_PCIE_CLR (0x77 << 3)
17 #define BOND_I2S_CLR 0x3
18 #define BOND_MSDC0E_CLR 0x1
21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
26 _x_bits, 16, 0)
29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
[all …]
Dpinctrl-mt2712.c20 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
22 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
25 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
27 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
29 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
[all …]
Dpinctrl-mt8173.c18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt8167.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8516.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8127.c20 /* 0E4E8SR 4/8/12/16 */
22 /* 0E2E4SR 2/4/6/8 */
25 MTK_DRV_GRP(2, 16, 0, 2, 2)
29 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
35 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
Dpinctrl-mt2701.c39 /* 0E4E8SR 4/8/12/16 */
41 /* 0E2E4SR 2/4/6/8 */
44 MTK_DRV_GRP(2, 16, 0, 2, 2)
48 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
54 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
Dpinctrl-mt7623.c13 #define PIN_BOND_REG0 0xb10
14 #define PIN_BOND_REG1 0xf20
15 #define PIN_BOND_REG2 0xef0
16 #define BOND_PCIE_CLR (0x77 << 3)
17 #define BOND_I2S_CLR 0x3
18 #define BOND_MSDC0E_CLR 0x1
21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
26 _x_bits, 16, 0)
29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
[all …]
Dpinctrl-mt2712.c21 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
22 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
23 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
24 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
25 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
26 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
29 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
30 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
31 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
[all …]
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7757.c30 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
31 DEFINE_RES_IRQ(evt2irq(0x700)),
36 .id = 0,
50 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
70 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
71 DEFINE_RES_IRQ(evt2irq(0xf00)),
89 DEFINE_RES_MEM(0xfe430000, 0x20),
90 DEFINE_RES_IRQ(evt2irq(0x580)),
91 DEFINE_RES_IRQ(evt2irq(0x5a0)),
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7757.c30 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
31 DEFINE_RES_IRQ(evt2irq(0x700)),
36 .id = 0,
50 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
70 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
71 DEFINE_RES_IRQ(evt2irq(0xf00)),
89 DEFINE_RES_MEM(0xfe430000, 0x20),
90 DEFINE_RES_IRQ(evt2irq(0x580)),
91 DEFINE_RES_IRQ(evt2irq(0x5a0)),
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi45 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu_atlas0: cpu@0 {
55 reg = <0x0>;
62 reg = <0x1>;
69 reg = <0x2>;
76 reg = <0x3>;
84 cpu_off = <0x84000002>;
85 cpu_on = <0xC4000003>;
88 soc: soc@0 {
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/qcom/
Dqcom,rpmh-rsc.yaml78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi45 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu_atlas0: cpu@0 {
55 reg = <0x0>;
57 i-cache-size = <0xc000>;
60 d-cache-size = <0x8000>;
69 reg = <0x1>;
71 i-cache-size = <0xc000>;
74 d-cache-size = <0x8000>;
83 reg = <0x2>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/
Drpmh-rsc.txt52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92 register offsets for DRV2 start at 0D00, the register calculations are like
94 DRV0: 0x179C0000
95 DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96 DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97 TCS-OFFSET: 0xD00
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
[all …]
/kernel/linux/linux-6.6/tools/perf/arch/powerpc/util/
Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/kernel/linux/linux-5.10/tools/perf/arch/powerpc/util/
Dbook3s_hv_exits.h10 {0x0, "RETURN_TO_HOST"}, \
11 {0x100, "SYSTEM_RESET"}, \
12 {0x200, "MACHINE_CHECK"}, \
13 {0x300, "DATA_STORAGE"}, \
14 {0x380, "DATA_SEGMENT"}, \
15 {0x400, "INST_STORAGE"}, \
16 {0x480, "INST_SEGMENT"}, \
17 {0x500, "EXTERNAL"}, \
18 {0x502, "EXTERNAL_HV"}, \
19 {0x600, "ALIGNMENT"}, \
[all …]
/kernel/linux/linux-6.6/arch/powerpc/kvm/
Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/kernel/linux/linux-5.10/arch/powerpc/kvm/
Dtrace_book3s.h10 {0x100, "SYSTEM_RESET"}, \
11 {0x200, "MACHINE_CHECK"}, \
12 {0x300, "DATA_STORAGE"}, \
13 {0x380, "DATA_SEGMENT"}, \
14 {0x400, "INST_STORAGE"}, \
15 {0x480, "INST_SEGMENT"}, \
16 {0x500, "EXTERNAL"}, \
17 {0x502, "EXTERNAL_HV"}, \
18 {0x600, "ALIGNMENT"}, \
19 {0x700, "PROGRAM"}, \
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/ti/icssg/
Dicssg_queues.c11 #define ICSSG_QUEUE_OFFSET 0xd00
12 #define ICSSG_QUEUE_PEEK_OFFSET 0xe00
13 #define ICSSG_QUEUE_CNT_OFFSET 0xe40
14 #define ICSSG_QUEUE_RESET_OFFSET 0xf40
45 return 0; in icssg_queue_level()

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