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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmarvell,prestera.txt21 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
23 packet-processor@0 {
25 reg = <0 0x4000000>;
45 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
46 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
73 that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:
76 ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
77 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
78 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
79 phys = <&cp0_comphy0 0>;
/kernel/linux/linux-5.10/arch/arm/mach-s3c/include/mach/
Dmap-base.h13 /* Fit all our registers in at 0xF6000000 upwards, trying to use as
21 #define S3C_ADDR_BASE 0xF6000000
29 #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
30 #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
31 #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
32 #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
33 #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
34 #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
40 #define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
Dmap-base.h13 /* Fit all our registers in at 0xF6000000 upwards, trying to use as
21 #define S3C_ADDR_BASE 0xF6000000
29 #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
30 #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
31 #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
32 #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
33 #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
34 #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
46 #define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Dhisilicon,kirin-pcie.yaml77 reg = <0x0 0xf4000000 0x0 0x1000>,
78 <0x0 0xff3fe000 0x0 0x1000>,
79 <0x0 0xf3f20000 0x0 0x40000>,
80 <0x0 0xf5000000 0x0 0x2000>;
82 bus-range = <0x0 0xff>;
86 ranges = <0x02000000 0x0 0x00000000
87 0x0 0xf6000000
88 0x0 0x02000000>;
91 interrupts = <0 283 4>;
93 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4/cpu/
Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
Dmmu_context.h10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
12 #define MMU_TTB 0xFF000008 /* Translation table base register */
13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
17 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
23 #define MMU_ITLB_DATA_ARRAY 0xF3000000
[all …]
/kernel/linux/linux-6.6/arch/sh/include/cpu-sh4/cpu/
Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
Dmmu_context.h10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
12 #define MMU_TTB 0xFF000008 /* Translation table base register */
13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
17 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
23 #define MMU_ITLB_DATA_ARRAY 0xF3000000
[all …]
/kernel/linux/linux-6.6/arch/arm/include/debug/
Ds5pv210.S9 #define S3C_ADDR_BASE 0xF6000000
10 #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
11 #define S5PV210_PA_UART 0xe2900000
22 #if CONFIG_DEBUG_S3C_UART != 0
23 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
24 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
Dexynos.S9 #define S3C_ADDR_BASE 0xF6000000
10 #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
11 #define EXYNOS4_PA_UART 0x13800000
12 #define EXYNOS5_PA_UART 0x12C00000
21 mrc p15, 0, \tmp, c0, c0, 0
22 and \tmp, \tmp, #0xf0
23 teq \tmp, #0xf0 @@ A15
25 mrc p15, 0, \tmp, c0, c0, 5
26 and \tmp, \tmp, #0xf00
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
[all …]
/kernel/linux/linux-5.10/arch/arm/include/debug/
Ds5pv210.S9 #define S3C_ADDR_BASE 0xF6000000
10 #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
11 #define S5PV210_PA_UART 0xe2900000
22 #if CONFIG_DEBUG_S3C_UART != 0
23 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
24 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
Dexynos.S9 #define S3C_ADDR_BASE 0xF6000000
10 #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
11 #define EXYNOS4_PA_UART 0x13800000
12 #define EXYNOS5_PA_UART 0x12C00000
21 mrc p15, 0, \tmp, c0, c0, 0
22 and \tmp, \tmp, #0xf0
23 teq \tmp, #0xf0 @@ A15
25 mrc p15, 0, \tmp, c0, c0, 5
26 and \tmp, \tmp, #0xf00
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-pxa/
Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
Dstandby.S27 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
35 #define PXA3_MDCNFG 0x0000
37 #define PXA3_DDR_HCAL 0x0060
38 #define PXA3_DDR_HCAL_HCRNG 0x1f
41 #define PXA3_DMCIER 0x0070
43 #define PXA3_DMCISR 0x0078
44 #define PXA3_RCOMP 0x0100
48 mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
49 add r1, r1, #0x00100000
61 mcr p14, 0, r0, c7, c0, 0
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-70x0.dtsi22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-70x0.dtsi22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
/kernel/linux/linux-5.10/arch/xtensa/configs/
Dxip_kc705_defconfig23 CONFIG_XIP_DATA_ADDR=0xd0000000
24 CONFIG_KERNEL_VIRTUAL_ADDRESS=0xe6000000
25 CONFIG_KERNEL_LOAD_ADDRESS=0xf6000000
30 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
/kernel/linux/linux-6.6/arch/xtensa/configs/
Dxip_kc705_defconfig23 CONFIG_XIP_DATA_ADDR=0xd0000000
24 CONFIG_KERNEL_VIRTUAL_ADDRESS=0xe6000000
25 CONFIG_KERNEL_LOAD_ADDRESS=0xf6000000
30 …arlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw …
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Dstandby.S30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
38 #define PXA3_MDCNFG 0x0000
40 #define PXA3_DDR_HCAL 0x0060
41 #define PXA3_DDR_HCAL_HCRNG 0x1f
44 #define PXA3_DMCIER 0x0070
46 #define PXA3_DMCISR 0x0078
47 #define PXA3_RCOMP 0x0100
51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
52 add r1, r1, #0x00100000
64 mcr p14, 0, r0, c7, c0, 0
[all …]

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