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/kernel/linux/linux-6.6/arch/arm64/boot/dts/intel/
Dsocfpga_agilex_n6000.dts26 reg = <0 0x80000000 0 0>;
32 reg = <0x80000000 0x60000000>,
33 <0xf9000000 0x00100000>;
37 ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
39 dma-controller@0 {
41 reg = <0x00000000 0x00000000 0x00001000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/intel/
Dintel,hps-copy-engine.yaml39 reg = <0x80000000 0x60000000>,
40 <0xf9000000 0x00100000>;
44 ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
46 dma-controller@0 {
48 reg = <0x00000000 0x00000000 0x00001000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmarvell,prestera.txt21 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
23 packet-processor@0 {
25 reg = <0 0x4000000>;
45 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
46 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
73 that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:
76 ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
77 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
78 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
79 phys = <&cp0_comphy0 0>;
/kernel/linux/linux-6.6/arch/arm/mach-footbridge/include/mach/
Dmemory.h22 #define FLUSH_BASE 0xf9000000
24 #define FLUSH_BASE_PHYS 0x50000000
Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-footbridge/include/mach/
Dmemory.h38 * The footbridge is programmed to expose the system RAM at 0xe0000000.
39 * The requirement is that the RAM isn't placed at bus address 0, which
42 #define BUS_OFFSET 0xe0000000
57 #define FLUSH_BASE 0xf9000000
59 #define FLUSH_BASE_PHYS 0x50000000
Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
[all …]
/kernel/linux/linux-6.6/arch/arc/boot/dts/
Dnsimosci.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
Dnsimosci_hs.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
Dnsimosci_hs_idu.dts18 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
34 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
56 interrupts = <0>;
65 #clock-cells = <0>;
72 reg = <0xf9000000 0x400>;
79 reg = <0xf9000400 0x14>;
87 reg = <0xf0003000 0x44>;
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dnsimosci.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
Dnsimosci_hs.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
Dnsimosci_hs_idu.dts18 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
34 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
56 interrupts = <0>;
65 #clock-cells = <0>;
72 reg = <0xf9000000 0x400>;
79 reg = <0xf9000400 0x14>;
87 reg = <0xf0003000 0x44>;
/kernel/linux/linux-6.6/arch/arm/mach-spear/
Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
Dspear13xx.c39 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
45 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
46 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
47 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
53 * 0xB3000000 0xF9000000
54 * 0xE0000000 0xFD000000
55 * 0xEC000000 0xFC000000
56 * 0xED000000 0xFB000000
/kernel/linux/linux-5.10/arch/arm/mach-spear/include/mach/
Dspear.h21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-spear/
Dspear13xx.c41 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
47 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
48 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
49 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
55 * 0xB3000000 0xF9000000
56 * 0xE0000000 0xFD000000
57 * 0xEC000000 0xFC000000
58 * 0xED000000 0xFB000000
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
DHalPhyRf_8723B.c12 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
14 #define IDX_0xC94 0
16 #define IDX_0xC14 0
18 #define KEY 0
22 #define PATH_S1 0 /* RF_PATH_A */
31 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
35 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
52 s32 ele_A = 0, ele_D, ele_C = 0, value32; in setIqkMatrix_8723B()
57 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; in setIqkMatrix_8723B()
60 if (IqkResult_X != 0) { in setIqkMatrix_8723B()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dphy.c91 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl8723be_phy_mac_config()
106 regval | BIT(13) | BIT(0) | BIT(1)); in rtl8723be_phy_bb_config()
112 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl8723be_phy_bb_config()
113 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl8723be_phy_bb_config()
115 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723be_phy_bb_config()
120 crystalcap = crystalcap & 0x3F; in rtl8723be_phy_bb_config()
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl8723be_phy_bb_config()
140 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); in _rtl8723be_check_positive()
142 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ in _rtl8723be_check_positive()
150 0 << 20 | /* interface 2/2 */ in _rtl8723be_check_positive()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Dphy.c91 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl8723be_phy_mac_config()
106 regval | BIT(13) | BIT(0) | BIT(1)); in rtl8723be_phy_bb_config()
112 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl8723be_phy_bb_config()
113 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl8723be_phy_bb_config()
115 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723be_phy_bb_config()
120 crystalcap = crystalcap & 0x3F; in rtl8723be_phy_bb_config()
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl8723be_phy_bb_config()
140 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); in _rtl8723be_check_positive()
142 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ in _rtl8723be_check_positive()
150 0 << 20 | /* interface 2/2 */ in _rtl8723be_check_positive()
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
DHalPhyRf_8723B.c18 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
20 #define IDX_0xC94 0
23 #define IDX_0xC14 0
25 #define KEY 0
29 #define PATH_S1 0 /* RF_PATH_A */
30 #define IDX_0xC9C 0
33 #define IDX_0xC1C 0
43 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
47 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
64 s32 ele_A = 0, ele_D, ele_C = 0, value32; in setIqkMatrix_8723B()
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/hal/
Dphy.c25 for (i = 0; i <= 31; i++) { in cal_bit_shift()
26 if (((bitmask >> i) & 0x1) == 1) in cal_bit_shift()
56 u32 ret = 0; in rf_serial_read()
59 u8 rfpi_enable = 0; in rf_serial_read()
61 offset &= 0xff; in rf_serial_read()
100 u32 data_and_addr = 0; in rf_serial_write()
103 offset &= 0xff; in rf_serial_write()
104 data_and_addr = ((offset << 20) | (data & 0x000fffff)) & 0x0fffffff; in rf_serial_write()
138 u8 TxCount = 0, path_nums; in get_tx_power_index()
142 for (TxCount = 0; TxCount < path_nums; TxCount++) { in get_tx_power_index()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]

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