Searched +full:0 +full:xfd000000 (Results 1 – 25 of 57) sorted by relevance
123
| /kernel/linux/linux-6.6/arch/arm/mach-spear/ |
| D | spear.h | 18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
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| D | spear3xx.c | 26 .bus_id = 0,
48 * 0xD0000000 0xFD000000
49 * 0xFC000000 0xFC000000
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| D | spear13xx.c | 39 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
45 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
46 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
47 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
53 * 0xB3000000 0xF9000000
54 * 0xE0000000 0xFD000000
55 * 0xEC000000 0xFC000000
56 * 0xED000000 0xFB000000
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| /kernel/linux/linux-5.10/arch/arm/mach-spear/include/mach/ |
| D | spear.h | 21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | vaddrs.h | 15 #define SRMMU_MAXMEM 0x0c000000
18 /* = 0x0fc000000 */
47 /* Leave one empty page between IO pages at 0xfd000000 and
50 #define FIXADDR_TOP (0xfcfff000UL)
56 #define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
57 #define IOBASE_VADDR 0xfe000000
58 #define IOBASE_END 0xfe600000
60 #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
61 #define KADB_DEBUGGER_ENDVM 0xffd00000
65 #define LINUX_OPPROM_BEGVM 0xffd00000
[all …]
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| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | vaddrs.h | 15 #define SRMMU_MAXMEM 0x0c000000
18 /* = 0x0fc000000 */
47 /* Leave one empty page between IO pages at 0xfd000000 and
50 #define FIXADDR_TOP (0xfcfff000UL)
56 #define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
57 #define IOBASE_VADDR 0xfe000000
58 #define IOBASE_END 0xfe600000
60 #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
61 #define KADB_DEBUGGER_ENDVM 0xffd00000
65 #define LINUX_OPPROM_BEGVM 0xffd00000
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-footbridge/include/mach/ |
| D | hardware.h | 13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-footbridge/include/mach/ |
| D | hardware.h | 13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
[all …]
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| /kernel/linux/linux-6.6/arch/sh/drivers/pci/ |
| D | pci-sh7751.h | 13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
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| D | pci-sh7780.h | 13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
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| D | pci-sh7780.c | 24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
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| /kernel/linux/linux-5.10/arch/sh/drivers/pci/ |
| D | pci-sh7751.h | 13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
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| D | pci-sh7780.h | 13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
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| D | pci-sh7780.c | 24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-davinci/ |
| D | hardware.h | 23 #define IO_PHYS UL(0x01c00000)
24 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
25 #define IO_SIZE 0x00400000
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| /kernel/linux/linux-5.10/arch/arm/mach-davinci/include/mach/ |
| D | hardware.h | 25 #define IO_PHYS UL(0x01c00000)
26 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
27 #define IO_SIZE 0x00400000
|
| /kernel/linux/linux-5.10/arch/arm/mach-ebsa110/ |
| D | core.h | 11 #define ISAMEM_PHYS 0xe0000000
12 #define ISAMEM_SIZE 0x10000000
14 #define ISAIO_PHYS 0xf0000000
17 #define TRICK0_PHYS 0xf2000000
19 #define TRICK1_PHYS 0xf2400000
21 #define TRICK2_PHYS 0xf2800000
22 #define TRICK3_PHYS 0xf2c00000
24 #define TRICK4_PHYS 0xf3000000
26 #define TRICK5_PHYS 0xf3400000
27 #define TRICK6_PHYS 0xf3800000
[all …]
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| /kernel/linux/linux-6.6/arch/xtensa/boot/dts/ |
| D | csp.dts | 11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
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| /kernel/linux/linux-5.10/arch/xtensa/boot/dts/ |
| D | csp.dts | 11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| D | renesas-scif.S | 12 #define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
16 #define FTDR 0x06
17 #define FSR 0x08
18 #elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
20 #define FTDR 0x20
21 #define FSR 0x14
24 #define FTDR 0x0c
25 #define FSR 0x10
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| /kernel/linux/linux-6.6/arch/arm/include/debug/ |
| D | renesas-scif.S | 12 #define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
16 #define FTDR 0x06
17 #define FSR 0x08
18 #elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
20 #define FTDR 0x20
21 #define FSR 0x14
24 #define FTDR 0x0c
25 #define FSR 0x10
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | rockchip,rk3399-pcie-ep.yaml | 50 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
63 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
67 pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-ep.txt | 27 - pinctrl-0: The "default" pinctrl state
31 where N ranges from 0 to 3.
51 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
58 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
59 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
61 pinctrl-0 = <&pcie_clkreq>;
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| /kernel/linux/linux-5.10/arch/arm/mach-spear/ |
| D | spear3xx.c | 28 .bus_id = 0,
60 * 0xD0000000 0xFD000000
61 * 0xFC000000 0xFC000000
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| D | spear13xx.c | 41 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()
47 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()
48 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()
49 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()
55 * 0xB3000000 0xF9000000
56 * 0xE0000000 0xFD000000
57 * 0xEC000000 0xFC000000
58 * 0xED000000 0xFB000000
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