Home
last modified time | relevance | path

Searched +full:0 +full:xfffffd00 (Results 1 – 19 of 19) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Datmel,at91sam9260-reset.yaml66 reg = <0xfffffd00 0x10>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Datmel-sysregs.txt39 reg = <0xfffffd00 0x10>;
55 reg = <0xffffe800 0x200>;
69 - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
85 reg = <0xfffffd10 0x10>;
114 Tree. Note also that input 0 is linked to the wake-up pin and is frequently
118 - reg: should contain the wake-up input index [0 - 15].
130 reg = <0xf8048010 0x10>;
133 #size-cells = <0>;
141 input@0 {
142 reg = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dat91sam9261.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x08000000>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
67 reg = <0x00300000 0x28000>;
70 ranges = <0 0x00300000 0x28000>;
[all …]
Dat91rm9200.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
73 reg = <0x00200000 0x4000>;
76 ranges = <0 0x00200000 0x4000>;
[all …]
Dat91sam9rl.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x04000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 reg = <0x00300000 0x10000>;
[all …]
Dat91sam9263.dtsi39 #size-cells = <0>;
41 cpu@0 {
44 reg = <0>;
50 reg = <0x20000000 0x08000000>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
69 reg = <0x00300000 0x14000>;
72 ranges = <0 0x00300000 0x14000>;
[all …]
Dat91sam9260.dtsi40 #size-cells = <0>;
42 cpu@0 {
45 reg = <0>;
51 reg = <0x20000000 0x04000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
76 reg = <0x002ff000 0x2000>;
[all …]
Dat91sam9g45.dtsi45 #size-cells = <0>;
47 cpu@0 {
50 reg = <0>;
56 reg = <0x70000000 0x10000000>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
69 clock-frequency = <0>;
74 #clock-cells = <0>;
81 reg = <0x00300000 0x10000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dat91sam9261.dtsi38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
[all …]
Dat91rm9200.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
[all …]
Dat91sam9rl.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
79 reg = <0x00300000 0x10000>;
[all …]
Dat91sam9260.dtsi41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x04000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 reg = <0x002ff000 0x2000>;
[all …]
Dat91sam9263.dtsi40 #size-cells = <0>;
42 cpu@0 {
45 reg = <0>;
51 reg = <0x20000000 0x08000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
70 reg = <0x00300000 0x14000>;
73 ranges = <0 0x00300000 0x14000>;
[all …]
Dat91sam9g45.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
57 reg = <0x70000000 0x10000000>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
69 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
82 reg = <0x00300000 0x10000>;
[all …]
/kernel/linux/linux-5.10/drivers/staging/vt6655/
Drf.c39 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
40 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
41 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
42 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
43 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
44 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
45 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
46 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
47 0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
48 0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
DMC68EZ328.h27 * 0xFFFFF0xx -- System Control
34 #define SCR_ADDR 0xfffff000
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
38 #define SCR_DMAP 0x04 /* Double Map */
39 #define SCR_SO 0x08 /* Supervisor Only */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
41 #define SCR_PRV 0x20 /* Privilege Violation */
42 #define SCR_WPV 0x40 /* Write Protect Violation */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
48 #define MRR_ADDR 0xfffff004
[all …]
DMC68VZ328.h29 * 0xFFFFF0xx -- System Control
36 #define SCR_ADDR 0xfffff000
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_DMAP 0x04 /* Double Map */
41 #define SCR_SO 0x08 /* Supervisor Only */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_PRV 0x20 /* Privilege Violation */
44 #define SCR_WPV 0x40 /* Write Protect Violation */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
50 #define MRR_ADDR 0xfffff004
[all …]
/kernel/linux/linux-6.6/arch/m68k/include/asm/
DMC68EZ328.h27 * 0xFFFFF0xx -- System Control
34 #define SCR_ADDR 0xfffff000
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
38 #define SCR_DMAP 0x04 /* Double Map */
39 #define SCR_SO 0x08 /* Supervisor Only */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
41 #define SCR_PRV 0x20 /* Privilege Violation */
42 #define SCR_WPV 0x40 /* Write Protect Violation */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
48 #define MRR_ADDR 0xfffff004
[all …]
DMC68VZ328.h29 * 0xFFFFF0xx -- System Control
36 #define SCR_ADDR 0xfffff000
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_DMAP 0x04 /* Double Map */
41 #define SCR_SO 0x08 /* Supervisor Only */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_PRV 0x20 /* Privilege Violation */
44 #define SCR_WPV 0x40 /* Write Protect Violation */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
50 #define MRR_ADDR 0xfffff004
[all …]