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/kernel/linux/linux-6.6/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
13 # v1.1 defined in version 1.1
19 module_model_id 0x0000 16
[all …]
/kernel/linux/linux-6.6/arch/arm64/crypto/
Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
37 * output: r0:r1 (low 128-bits in r0, high in r1)
40 ext T0.16b, m1.16b, m1.16b, #8; \
41 pmull r0.1q, m0.1d, m1.1d; \
42 pmull T1.1q, m0.1d, T0.1d; \
43 pmull2 T0.1q, m0.2d, T0.2d; \
[all …]
Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
64 pmull \rd\().1q, \rn\().1d, \rm\().1d
68 pmull2 \rd\().1q, \rn\().2d, \rm\().2d
72 ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
80 tbl t3.16b, {\ad\().16b}, perm1.16b // A1
81 tbl t5.16b, {\ad\().16b}, perm2.16b // A2
82 tbl t7.16b, {\ad\().16b}, perm3.16b // A3
96 __pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
[all …]
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
19 ld1 {v0.16b}, [x0] /* load mac */
20 cbz w3, 1f
21 sub w3, w3, #16
22 eor v1.16b, v1.16b, v1.16b
23 0: ldrb w7, [x1], #1 /* get 1 byte of input */
24 subs w2, w2, #1
[all …]
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
17 .set .Lv\b\().16b, \b
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
[all …]
Dpolyval-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * ..., h^1 in the POLYVAL finite field. This precomputation allows us to split
14 * than 128. We then compute p(x) = h^8m_0 + ... + h^1m_7 where multiplication
18 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
20 * This two step process is equivalent to computing h^8m_0 + ... + h^1m_7 where
22 * two-step process only requires 1 finite field reduction for every 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
84 * Later, the 256-bit result can be extracted as:
[all …]
Dsm4-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-CCM AEAD Algorithm using ARMv8 Crypto Extensions
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31
32 mov vctr.d[1], x8; \
34 adds x8, x8, #1; \
35 rev64 vctr.16b, vctr.16b; \
49 ld1 {RMAC.16b}, [x1]
57 ld1 {v0.16b-v3.16b}, [x2], #64
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
89 ext v5.16b, v5.16b, v5.16b, #8
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
60 .arch armv8-a+crypto
63 pmull \rd\().1q, \rn\().1d, \rm\().1d
67 pmull2 \rd\().1q, \rn\().2d, \rm\().2d
71 ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
79 tbl t3.16b, {\ad\().16b}, perm1.16b // A1
80 tbl t5.16b, {\ad\().16b}, perm2.16b // A2
81 tbl t7.16b, {\ad\().16b}, perm3.16b // A3
95 __pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
[all …]
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
17 .set .Lv\b\().16b, \b
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
[all …]
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
20 ld1 {v0.16b}, [x0] /* load mac */
21 cbz w8, 1f
22 sub w8, w8, #16
23 eor v1.16b, v1.16b, v1.16b
24 0: ldrb w7, [x1], #1 /* get 1 byte of input */
25 subs w2, w2, #1
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
89 ext v5.16b, v5.16b, v5.16b, #8
[all …]
Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
191 in_bs_ch \b0\().16b, \b1\().16b, \b2\().16b, \b3\().16b, \
192 \b4\().16b, \b5\().16b, \b6\().16b, \b7\().16b
193 inv_gf256 \b6\().16b, \b5\().16b, \b0\().16b, \b3\().16b, \
194 \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
195 \t0\().16b, \t1\().16b, \t2\().16b, \t3\().16b, \
196 \s0\().16b, \s1\().16b, \s2\().16b, \s3\().16b
197 out_bs_ch \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
[all …]
/kernel/linux/linux-5.10/arch/alpha/kernel/
Dsys_takara.c1 // SPDX-License-Identifier: GPL-2.0
34 static unsigned long cached_irq_mask[2] = { -1, -1 };
41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw()
42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw()
49 unsigned int irq = d->irq; in takara_enable_irq()
51 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); in takara_enable_irq()
58 unsigned int irq = d->irq; in takara_disable_irq()
60 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); in takara_disable_irq()
99 if (intstatus & 8) handle_irq(16+3); in takara_device_interrupt()
100 if (intstatus & 4) handle_irq(16+2); in takara_device_interrupt()
[all …]
Dsys_rx164.c1 // SPDX-License-Identifier: GPL-2.0
51 rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); in rx164_enable_irq()
57 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); in rx164_disable_irq()
85 pld &= pld - 1; /* clear least bit set */ in rx164_device_interrupt()
89 handle_irq(16+i); in rx164_device_interrupt()
100 for (i = 16; i < 40; ++i) { in rx164_init_irq()
108 if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL)) in rx164_init_irq()
109 pr_err("Failed to register isa-cascade interrupt\n"); in rx164_init_irq()
120 * 1 7 4 9 14 19
123 * 4 10 1 6 11 16
[all …]
Dsys_miata.c1 // SPDX-License-Identifier: GPL-2.0
39 irq = (vector - 0x800) >> 4; in miata_srm_device_interrupt()
47 * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't in miata_srm_device_interrupt()
49 * vectors 0x800-0x8f0). in miata_srm_device_interrupt()
53 * So, here's this grotty hack... :-( in miata_srm_device_interrupt()
55 if (irq >= 16) in miata_srm_device_interrupt()
76 NMI (1), or EIDE (9). in miata_init_irq()
83 if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL)) in miata_init_irq()
84 pr_err("Failed to register halt-switch interrupt\n"); in miata_init_irq()
85 if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) in miata_init_irq()
[all …]
Dsys_noritake.c1 // SPDX-License-Identifier: GPL-2.0
44 mask >>= 16; in noritake_update_irq_hw()
53 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); in noritake_enable_irq()
59 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); in noritake_disable_irq()
77 | ((unsigned long) inw(0x54a) << 16) in noritake_device_interrupt()
87 pld &= pld - 1; /* clear least bit set */ in noritake_device_interrupt()
88 if (i < 16) { in noritake_device_interrupt()
101 irq = (vector - 0x800) >> 4; in noritake_srm_device_interrupt()
110 * So, here's this additional grotty hack... :-( in noritake_srm_device_interrupt()
112 if (irq >= 16) in noritake_srm_device_interrupt()
[all …]
Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
43 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
44 outb(mask >> (16 + ofs * 8), 0x804 + ofs); in cabriolet_update_irq_hw()
50 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
56 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
73 pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16); in cabriolet_device_interrupt()
81 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
85 handle_irq(16 + i); in cabriolet_device_interrupt()
106 for (i = 16; i < 35; ++i) { in common_init_irq()
114 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
[all …]
/kernel/linux/linux-6.6/arch/alpha/kernel/
Dsys_takara.c1 // SPDX-License-Identifier: GPL-2.0
34 static unsigned long cached_irq_mask[2] = { -1, -1 };
41 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); in takara_update_irq_hw()
42 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); in takara_update_irq_hw()
49 unsigned int irq = d->irq; in takara_enable_irq()
51 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); in takara_enable_irq()
58 unsigned int irq = d->irq; in takara_disable_irq()
60 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); in takara_disable_irq()
99 if (intstatus & 8) handle_irq(16+3); in takara_device_interrupt()
100 if (intstatus & 4) handle_irq(16+2); in takara_device_interrupt()
[all …]
Dsys_rx164.c1 // SPDX-License-Identifier: GPL-2.0
51 rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); in rx164_enable_irq()
57 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); in rx164_disable_irq()
85 pld &= pld - 1; /* clear least bit set */ in rx164_device_interrupt()
89 handle_irq(16+i); in rx164_device_interrupt()
100 for (i = 16; i < 40; ++i) { in rx164_init_irq()
108 if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL)) in rx164_init_irq()
109 pr_err("Failed to register isa-cascade interrupt\n"); in rx164_init_irq()
120 * 1 7 4 9 14 19
123 * 4 10 1 6 11 16
[all …]
Dsys_miata.c1 // SPDX-License-Identifier: GPL-2.0
39 irq = (vector - 0x800) >> 4; in miata_srm_device_interrupt()
47 * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't in miata_srm_device_interrupt()
49 * vectors 0x800-0x8f0). in miata_srm_device_interrupt()
53 * So, here's this grotty hack... :-( in miata_srm_device_interrupt()
55 if (irq >= 16) in miata_srm_device_interrupt()
76 NMI (1), or EIDE (9). in miata_init_irq()
83 if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL)) in miata_init_irq()
84 pr_err("Failed to register halt-switch interrupt\n"); in miata_init_irq()
85 if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) in miata_init_irq()
[all …]
Dsys_noritake.c1 // SPDX-License-Identifier: GPL-2.0
44 mask >>= 16; in noritake_update_irq_hw()
53 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); in noritake_enable_irq()
59 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); in noritake_disable_irq()
77 | ((unsigned long) inw(0x54a) << 16) in noritake_device_interrupt()
87 pld &= pld - 1; /* clear least bit set */ in noritake_device_interrupt()
88 if (i < 16) { in noritake_device_interrupt()
101 irq = (vector - 0x800) >> 4; in noritake_srm_device_interrupt()
110 * So, here's this additional grotty hack... :-( in noritake_srm_device_interrupt()
112 if (irq >= 16) in noritake_srm_device_interrupt()
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Daes-gcm-p10.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
52 xxlor 19+32, 1, 1
[all …]
/kernel/linux/linux-5.10/arch/alpha/lib/
Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]
/kernel/linux/linux-6.6/arch/alpha/lib/
Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]

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