| /kernel/linux/linux-6.6/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpkg.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
33 DPKG_FROM_FIELD = 1,
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
47 DPKG_EXTRACT_FROM_DATA = 1,
52 * struct dpkg_mask - A structure for defining a single extraction mask
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| /kernel/linux/linux-5.10/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpkg.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
25 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
32 DPKG_FROM_FIELD = 1,
37 * enum dpkg_extract_type - Enumeration for selecting extraction type
40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
46 DPKG_EXTRACT_FROM_DATA = 1,
51 * struct dpkg_mask - A structure for defining a single extraction mask
63 #define NH_FLD_ETH_DA BIT(0)
64 #define NH_FLD_ETH_SA BIT(1)
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| /kernel/linux/linux-6.6/drivers/net/dsa/microchip/ |
| D | ksz9477_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
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| D | lan937x_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
8 #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
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| /kernel/linux/linux-5.10/drivers/net/dsa/microchip/ |
| D | ksz9477_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
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| D | ksz8795_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 #define SW_REVISION_S 1
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
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| /kernel/linux/linux-5.10/drivers/net/ethernet/marvell/ |
| D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
137 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
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| D | sky2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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| /kernel/linux/linux-6.6/drivers/net/ethernet/marvell/ |
| D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
137 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
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| D | sky2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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| /kernel/linux/linux-5.10/drivers/net/fddi/skfp/h/ |
| D | skfbi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
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| /kernel/linux/linux-6.6/drivers/net/fddi/skfp/h/ |
| D | skfbi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_display_device.c | 1 // SPDX-License-Identifier: MIT
34 /* ICL DSI 0 and 1 */
174 .has_overlay = 1, \
175 .cursor_needs_physical = 1, \
176 .overlay_needs_physical = 1, \
177 .has_gmch = 1, \
183 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
185 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
188 .has_overlay = 1, \
189 .overlay_needs_physical = 1, \
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| /kernel/linux/linux-6.6/drivers/net/wireless/ath/wil6210/ |
| D | txrx.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
13 #define BUF_SW_OWNED (1)
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
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| D | txrx_edma.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
22 #define WIL_TX_STATUS_IRQ_IDX 1
28 #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */
31 #define WIL_RX_EDMA_ERROR_MIC (1)
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
55 #define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1
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| /kernel/linux/linux-5.10/drivers/net/wireless/ath/wil6210/ |
| D | txrx.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
13 #define BUF_SW_OWNED (1)
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
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| D | txrx_edma.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
22 #define WIL_TX_STATUS_IRQ_IDX 1
28 #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */
31 #define WIL_RX_EDMA_ERROR_MIC (1)
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
55 #define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1
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| /kernel/linux/linux-5.10/drivers/gpu/drm/meson/ |
| D | meson_dw_hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
19 * Default 1.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
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| /kernel/linux/linux-6.6/drivers/gpu/drm/meson/ |
| D | meson_dw_hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
19 * Default 1.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/ |
| D | rcar_du_drv.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
32 /* -----------------------------------------------------------------------------
41 .channels_mask = BIT(1) | BIT(0),
47 .possible_crtcs = BIT(1) | BIT(0),
51 .possible_crtcs = BIT(0),
52 .port = 1,
55 .num_lvds = 1,
63 .channels_mask = BIT(1) | BIT(0),
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| /kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_du_drv.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
31 /* -----------------------------------------------------------------------------
41 .channels_mask = BIT(1) | BIT(0),
47 .possible_crtcs = BIT(1) | BIT(0),
51 .possible_crtcs = BIT(0),
52 .port = 1,
55 .num_lvds = 1,
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| /kernel/linux/linux-6.6/drivers/staging/emxx_udc/ |
| D | emxx_udc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 /*---------------------------------------------------------------------------*/
13 /*----------------- Default define */
14 #define USE_DMA 1
15 #define USE_SUSPEND_WAIT 1
17 /*------------ Board dependence(Resource) */
24 /*------------ Board dependence(Wait) */
27 #define VBUS_CHATTERING_MDELAY 1
31 /*------------ Controller dependence */
36 #define EPC_RST_DISABLE_TIME 1 /* 1 usec */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/cortina/ |
| D | gemini.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
57 #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
91 /* GMAC 0/1 DMA/TOE register */
148 /* TOE GMAC 0/1 register */
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| /kernel/linux/linux-6.6/drivers/net/ethernet/cortina/ |
| D | gemini.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
57 #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
91 /* GMAC 0/1 DMA/TOE register */
148 /* TOE GMAC 0/1 register */
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| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | ni_stc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
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