| /kernel/linux/linux-6.6/drivers/isdn/mISDN/ |
| D | layer2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
59 #define L2_EVENT_COUNT (EV_L2_FRAME_ERROR + 1)
92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
[all …]
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| D | tei.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #define ID_REQUEST 1
39 #define DEACT_STATE_COUNT (ST_L1_ACTIV + 1)
57 #define DEACT_EVENT_COUNT (EV_DATIMER + 1)
72 struct manager *mgr = fi->userdata; in da_debug()
84 printk(KERN_DEBUG "mgr(%d): %pV\n", mgr->ch.st->dev->id, &vaf); in da_debug()
92 struct manager *mgr = fi->userdata; in da_activate()
94 if (fi->state == ST_L1_DEACT_PENDING) in da_activate()
95 mISDN_FsmDelTimer(&mgr->datimer, 1); in da_activate()
108 struct manager *mgr = fi->userdata; in da_deactivate()
[all …]
|
| /kernel/linux/linux-5.10/drivers/isdn/mISDN/ |
| D | layer2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
59 #define L2_EVENT_COUNT (EV_L2_FRAME_ERROR + 1)
92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
[all …]
|
| D | tei.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #define ID_REQUEST 1
39 #define DEACT_STATE_COUNT (ST_L1_ACTIV + 1)
57 #define DEACT_EVENT_COUNT (EV_DATIMER + 1)
72 struct manager *mgr = fi->userdata; in da_debug()
84 printk(KERN_DEBUG "mgr(%d): %pV\n", mgr->ch.st->dev->id, &vaf); in da_debug()
92 struct manager *mgr = fi->userdata; in da_activate()
94 if (fi->state == ST_L1_DEACT_PENDING) in da_activate()
95 mISDN_FsmDelTimer(&mgr->datimer, 1); in da_activate()
108 struct manager *mgr = fi->userdata; in da_deactivate()
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 3 "CollectPEBSRecord": "1",
4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
6 "Counter": "0,1,2,3",
10 "BriefDescription": "L2 cache request misses"
13 "CollectPEBSRecord": "1",
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
16 "Counter": "0,1,2,3",
20 "BriefDescription": "L2 cache requests"
23 "CollectPEBSRecord": "1",
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
50 "Data_LA": "1",
54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
60 "Data_LA": "1",
70 "Data_LA": "1",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
50 "Data_LA": "1",
54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
60 "Data_LA": "1",
70 "Data_LA": "1",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
12 "CounterMask": "1",
22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
28 "CounterMask": "1",
36 "AnyThread": "1",
38 "CounterMask": "1",
45 "BriefDescription": "Not rejected writebacks that hit L2 cache",
48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
53 "BriefDescription": "L2 cache lines filling L2",
56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 3 "CollectPEBSRecord": "1",
4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
6 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
12 "BriefDescription": "L2 cache request misses"
15 "CollectPEBSRecord": "1",
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
18 "Counter": "0,1,2,3",
20 "PEBScounters": "0,1,2,3",
24 "BriefDescription": "L2 cache requests"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | cache.json | 12 "CounterMask": "1",
22 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
28 "CounterMask": "1",
35 "AnyThread": "1",
37 "CounterMask": "1",
51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 12 "CounterMask": "1",
22 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
28 "CounterMask": "1",
35 "AnyThread": "1",
37 "CounterMask": "1",
51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
20 "CounterMask": "1",
21 "EdgeDetect": "1",
29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
46 "CounterMask": "1",
54 "BriefDescription": "L2 cache lines filling L2",
57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
62 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 12 "CounterMask": "1",
23 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
29 "CounterMask": "1",
36 "AnyThread": "1",
38 "CounterMask": "1",
46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
12 "CounterMask": "1",
22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
28 "CounterMask": "1",
36 "AnyThread": "1",
38 "CounterMask": "1",
45 "BriefDescription": "Not rejected writebacks that hit L2 cache",
48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
53 "BriefDescription": "L2 cache lines filling L2",
56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | cache.json | 4 "Counter": "0,1",
8 …ing SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC)…
12 "Counter": "0,1",
16 …at were not accepted into the L2Q because of any L2 queue reject condition. There is no concept o…
20 "Counter": "0,1",
24 "BriefDescription": "Counts the total number of L2 cache references."
28 "Counter": "0,1",
32 "BriefDescription": "Counts the number of L2 cache misses"
37 "Counter": "0,1",
44 …"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 5 "BriefDescription": "Demand Data Read miss L2, no rejects",
6 "Counter": "0,1,2,3",
8 …ion": "This event counts the number of demand Data Read requests that miss L2 cache. Only not reje…
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
15 "BriefDescription": "RFO requests that miss L2 cache.",
16 "Counter": "0,1,2,3",
19 "CounterHTOff": "0,1,2,3,4,5,6,7"
24 "BriefDescription": "L2 cache misses when fetching instructions.",
25 "Counter": "0,1,2,3",
28 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | cache.json | 12 "CounterMask": "1",
23 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur…
29 "CounterMask": "1",
36 "AnyThread": "1",
38 "CounterMask": "1",
46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | cache.json | 13 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
27 "CounterMask": "1",
28 "EdgeDetect": "1",
37 "Deprecated": "1",
44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
47 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
61 "CounterMask": "1",
69 "BriefDescription": "L2 cache lines filling L2",
72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | cache.json | 3 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
5 "Counter": "0,1",
9 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ"
12 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
14 "Counter": "0,1",
21 …his event counts requests originating from the core that references a cache line in the L2 cache.",
23 "Counter": "0,1",
27 "BriefDescription": "L2 cache requests from this core"
30 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
32 "Counter": "0,1",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
5 "Counter": "0,1,2,3",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
15 "Counter": "0,1,2,3",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
23 "PublicDescription": "RFO requests that hit L2 cache.",
25 "Counter": "0,1,2,3",
29 "BriefDescription": "RFO requests that hit L2 cache",
[all …]
|