| /kernel/linux/linux-5.10/Documentation/i2c/ |
| D | ten-bit-addresses.rst | 2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
17 The current 10 bit address support is minimal. It should work, however
[all …]
|
| /kernel/linux/linux-6.6/Documentation/i2c/ |
| D | ten-bit-addresses.rst | 2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
17 The current 10 bit address support is minimal. It should work, however
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
[all …]
|
| /kernel/linux/linux-6.6/Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
111 Cross-device interoperability
115 canonical formats for use between AFBC-enabled devices. Formats which
119 .. flat-table:: AFBC formats
121 * - Fourcc code
122 - Description
[all …]
|
| /kernel/linux/linux-5.10/Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
111 Cross-device interoperability
115 canonical formats for use between AFBC-enabled devices. Formats which
119 .. flat-table:: AFBC formats
121 * - Fourcc code
122 - Description
[all …]
|
| /kernel/linux/linux-6.6/scripts/gdb/linux/ |
| D | pgtable.py | 1 # SPDX-License-Identifier: GPL-2.0-only
44 return (bit_start, bit_end), data >> bit_start & ((1 << (1 + bit_end - bit_start)) - 1)
82 ---
83 …{'bit' : <4} {self.page_level_write_through[0]: <10} {'page level write through': <30} {self.page_…
84 …{'bit' : <4} {self.page_level_cache_disabled[0]: <10} {'page level cache disabled': <30} {self.pag…
140 next_level = self.page_hierarchy_level - 1
150 ---
155 return "" if level == 1 else f"{'bit': <3} {ps_bit: <5} {'page size': <30} {ps}"
163 ---
164 {'bit': <4} {self.entry_present[0]: <10} {'entry present': <30} {self.entry_present[1]}
[all …]
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| /kernel/linux/linux-6.6/drivers/comedi/drivers/ |
| D | ni_at_ao.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | ni_at_ao.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/ath/wil6210/ |
| D | txrx.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/ath/wil6210/ |
| D | txrx.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/asix/ |
| D | ax88796c_main.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/dec/tulip/ |
| D | pnic2.c | 5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
30 * Bit 11:10 - Loop Back Operation Mode
31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/dec/tulip/ |
| D | pnic2.c | 5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
30 * Bit 11:10 - Loop Back Operation Mode
31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ |
| D | mipi_backend_common_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/ |
| D | css_receiver_2400_common_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
|
| /kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/ |
| D | css_receiver_2400_common_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
|
| /kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ |
| D | mipi_backend_common_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/marvell/ |
| D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/marvell/ |
| D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
[all …]
|
| /kernel/linux/linux-6.6/include/uapi/linux/ |
| D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
38 #define MDIO_CTRL2 7 /* 10G control 2 */
39 #define MDIO_STAT2 8 /* 10G status 2 */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/meson/ |
| D | meson_dw_hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/meson/ |
| D | meson_dw_hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/ |
| D | mt76_connac2_mac.h | 1 /* SPDX-License-Identifier: ISC */
41 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
63 #define MT_TXD2_FIXED_RATE BIT(30)
67 #define MT_TXD2_HTC_VLD BIT(13)
[all …]
|
| /kernel/linux/linux-6.6/include/soc/mscc/ |
| D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
|
| /kernel/linux/linux-5.10/include/soc/mscc/ |
| D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
|