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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml39 # (one for the internal 100base-T1 PHYs and the other for the single
40 # 100base-TX PHY). The "reg" property does not have physical significance.
41 # The PHY addresses to port correspondence is as follows: for 100base-T1,
42 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
91 rx-internal-delay-ps:
92 $ref: "#/$defs/internal-delay-ps"
93 tx-internal-delay-ps:
94 $ref: "#/$defs/internal-delay-ps"
101 internal-delay-ps:
103 Disable tunable delay lines using 0 ps, or enable them and select
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmicrel-ksz90x1.txt15 value is 0, the maximum value is 3000, and it can be specified in 200ps
17 skew values actually increase in 120ps steps, starting from -840ps. The
29 0 -840ps 0000
30 200 -720ps 0001
31 400 -600ps 0010
32 600 -480ps 0011
33 800 -360ps 0100
34 1000 -240ps 0101
35 1200 -120ps 0110
36 1400 0ps 0111
[all …]
Dti,dp83869.yaml18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
67 rx-internal-delay-ps:
73 tx-internal-delay-ps:
97 rx-internal-delay-ps = <2000>;
98 tx-internal-delay-ps = <2000>;
Dti,dp83822.yaml14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
49 100base-fx (full and half duplex) modes.
51 rx-internal-delay-ps:
58 tx-internal-delay-ps:
77 rx-internal-delay-ps = <1>;
78 tx-internal-delay-ps = <1>;
Dallwinner,sun8i-a83t-emac.yaml73 allwinner,tx-delay-ps:
77 multipleOf: 100
79 External RGMII PHY TX clock delay chain value in ps.
81 allwinner,rx-delay-ps:
85 multipleOf: 100
87 External RGMII PHY TX clock delay chain value in ps.
98 allwinner,rx-delay-ps:
102 multipleOf: 100
104 External RGMII PHY TX clock delay chain value in ps.
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmicrel-ksz90x1.txt15 value is 0, the maximum value is 3000, and it can be specified in 200ps
17 skew values actually increase in 120ps steps, starting from -840ps. The
29 0 -840ps 0000
30 200 -720ps 0001
31 400 -600ps 0010
32 600 -480ps 0011
33 800 -360ps 0100
34 1000 -240ps 0101
35 1200 -120ps 0110
36 1400 0ps 0111
[all …]
Dti,dp83869.yaml18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
67 rx-internal-delay-ps:
73 tx-internal-delay-ps:
97 rx-internal-delay-ps = <2000>;
98 tx-internal-delay-ps = <2000>;
Dti,dp83822.yaml14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
49 100base-fx (full and half duplex) modes.
51 rx-internal-delay-ps:
58 tx-internal-delay-ps:
77 rx-internal-delay-ps = <1>;
78 tx-internal-delay-ps = <1>;
Dallwinner,sun8i-a83t-emac.yaml79 allwinner,tx-delay-ps:
83 multipleOf: 100
85 External RGMII PHY TX clock delay chain value in ps.
87 allwinner,rx-delay-ps:
91 multipleOf: 100
93 External RGMII PHY TX clock delay chain value in ps.
104 allwinner,rx-delay-ps:
108 multipleOf: 100
110 External RGMII PHY TX clock delay chain value in ps.
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7110-starfive-visionfive-2-v1.3b.dts29 motorcomm,tx-clk-100-inverted;
33 rx-internal-delay-ps = <1500>;
34 tx-internal-delay-ps = <1500>;
39 motorcomm,tx-clk-100-inverted;
42 rx-internal-delay-ps = <300>;
43 tx-internal-delay-ps = <0>;
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx6q-mba6.dtsi16 rxdv-skew-ps = <180>;
17 txen-skew-ps = <120>;
18 rxd3-skew-ps = <180>;
19 rxd2-skew-ps = <180>;
20 rxd1-skew-ps = <180>;
21 rxd0-skew-ps = <180>;
22 txd3-skew-ps = <120>;
23 txd2-skew-ps = <0>;
24 txd1-skew-ps = <180>;
25 txd0-skew-ps = <360>;
[all …]
/kernel/linux/linux-6.6/arch/parisc/kernel/
Dhardware.c48 {HPHW_NPROC,0x182,0x4,0x91,"TNT 100 (891,T500)"},
78 {HPHW_NPROC,0x317,0x4,0x81,"Scorpio 100 (715/100)"},
81 {HPHW_NPROC,0x320,0x4,0x81,"Spectra (725/100)"},
89 {HPHW_NPROC,0x484,0x4,0x81,"UL Proc L-100 (811/D210,D310)"},
113 {HPHW_NPROC,0x580,0x4,0x81,"KittyHawk DC2-100 (K100)"},
115 {HPHW_NPROC,0x582,0x4,0x91,"KittyHawk DC3 100 (K400)"},
118 {HPHW_NPROC,0x585,0x4,0x91,"SkyHawk 100"},
122 {HPHW_NPROC,0x589,0x4,0x81,"UL Proc 1-way T'100 (821/D250,D350)"},
123 {HPHW_NPROC,0x58A,0x4,0x91,"UL Proc 2-way T'100 (831/D250,D350)"},
124 {HPHW_NPROC,0x58B,0x4,0x91,"KittyHawk DC2 100 (K200)"},
[all …]
/kernel/linux/linux-5.10/arch/parisc/kernel/
Dhardware.c51 {HPHW_NPROC,0x182,0x4,0x91,"TNT 100 (891,T500)"},
81 {HPHW_NPROC,0x317,0x4,0x81,"Scorpio 100 (715/100)"},
84 {HPHW_NPROC,0x320,0x4,0x81,"Spectra (725/100)"},
92 {HPHW_NPROC,0x484,0x4,0x81,"UL Proc L-100 (811/D210,D310)"},
116 {HPHW_NPROC,0x580,0x4,0x81,"KittyHawk DC2-100 (K100)"},
118 {HPHW_NPROC,0x582,0x4,0x91,"KittyHawk DC3 100 (K400)"},
121 {HPHW_NPROC,0x585,0x4,0x91,"SkyHawk 100"},
125 {HPHW_NPROC,0x589,0x4,0x81,"UL Proc 1-way T'100 (821/D250,D350)"},
126 {HPHW_NPROC,0x58A,0x4,0x91,"UL Proc 2-way T'100 (831/D250,D350)"},
127 {HPHW_NPROC,0x58B,0x4,0x91,"KittyHawk DC2 100 (K200)"},
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Dsumo_dpm.c76 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps() local
78 return ps; in sumo_get_ps()
135 u32 grs = 256 * 25 / 100; in sumo_program_grsd()
320 pi->pasi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
321 pi->asi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
345 struct sumo_ps *ps = sumo_get_ps(rps); in sumo_program_bsp() local
347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
349 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
354 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
359 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dsumo_dpm.c76 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps() local
78 return ps; in sumo_get_ps()
135 u32 grs = 256 * 25 / 100; in sumo_program_grsd()
320 pi->pasi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
321 pi->asi = 65535 * 100 / high_clk; in sumo_calculate_bsp()
345 struct sumo_ps *ps = sumo_get_ps(rps); in sumo_program_bsp() local
347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
349 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
354 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
359 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) in sumo_program_bsp()
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/mm/
Dthuge-gen.c78 void show(unsigned long ps) in show() argument
80 char buf[100]; in show()
81 if (ps == getpagesize()) in show()
83 printf("%luMB: ", ps >> 20); in show()
87 ps >> 10); in show()
95 char buf[100]; in read_sysfs()
118 unsigned long read_free(unsigned long ps) in read_free() argument
120 return read_sysfs(ps != getpagesize(), in read_free()
122 ps >> 10); in read_free()
219 unsigned long ps = page_sizes[i]; in main() local
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8mp-dhcom-pdk2.dts7 * DHCOM PCB number: 660-100 or newer
162 max-speed = <100>;
167 rxc-skew-ps = <3000>;
168 rxd0-skew-ps = <0>;
169 rxd1-skew-ps = <0>;
170 rxd2-skew-ps = <0>;
171 rxd3-skew-ps = <0>;
172 rxdv-skew-ps = <0>;
173 txc-skew-ps = <3000>;
174 txd0-skew-ps = <0>;
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/vm/
Dthuge-gen.c95 void show(unsigned long ps) in show() argument
97 char buf[100]; in show()
98 if (ps == getpagesize()) in show()
100 printf("%luMB: ", ps >> 20); in show()
104 ps >> 10); in show()
112 char buf[100]; in read_sysfs()
135 unsigned long read_free(unsigned long ps) in read_free() argument
137 return read_sysfs(ps != getpagesize(), in read_free()
139 ps >> 10); in read_free()
236 unsigned long ps = page_sizes[i]; in main() local
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Dps.c8 #include "ps.h"
98 udelay(100); in rtw_power_mode_change()
102 rtw_warn(rtwdev, "failed to leave deep PS, retry=%d\n", in rtw_power_mode_change()
131 * PS bit could be sent due to incorrect REG_TCR setting. in rtw_fw_leave_lps_state_check()
133 * In our test, 100ms should be enough for firmware to finish in rtw_fw_leave_lps_state_check()
134 * the flow. If REG_TCR Register is still incorrect after 100ms, in rtw_fw_leave_lps_state_check()
172 "Should enter LPS before entering deep PS\n"); in __rtw_enter_lps_deep()
218 "Should leave deep PS before leaving LPS\n"); in __rtw_leave_lps()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
263 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { in smu10_set_soft_max_gfxclk_by_freq()
264 smu10_data->gfx_max_freq_limit = clock * 100; in smu10_set_soft_max_gfxclk_by_freq()
448 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; in smu10_get_clock_voltage_dependency_table()
555 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100; in smu10_hwmgr_backend_init()
556 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100; in smu10_hwmgr_backend_init()
596 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
608 min_sclk /= 100; /* transfer 10KHz to MHz */ in smu10_dpm_force_dpm_level()
617 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
634 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10_socdk.dtsi74 * These skews assume the user's FPGA design is adding 600ps of delay
81 txd0-skew-ps = <0>; /* -420ps */
82 txd1-skew-ps = <0>; /* -420ps */
83 txd2-skew-ps = <0>; /* -420ps */
84 txd3-skew-ps = <0>; /* -420ps */
85 rxd0-skew-ps = <420>; /* 0ps */
86 rxd1-skew-ps = <420>; /* 0ps */
87 rxd2-skew-ps = <420>; /* 0ps */
88 rxd3-skew-ps = <420>; /* 0ps */
89 txen-skew-ps = <0>; /* -420ps */
[all …]
Dsocfpga_arria5_socdk.dts65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txen-skew-ps = <0>;
70 txc-skew-ps = <2600>;
71 rxdv-skew-ps = <0>;
72 rxc-skew-ps = <2000>;
93 * because the LCD module does not work at the standard 100Khz
/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10_socdk.dtsi74 * These skews assume the user's FPGA design is adding 600ps of delay
81 txd0-skew-ps = <0>; /* -420ps */
82 txd1-skew-ps = <0>; /* -420ps */
83 txd2-skew-ps = <0>; /* -420ps */
84 txd3-skew-ps = <0>; /* -420ps */
85 rxd0-skew-ps = <420>; /* 0ps */
86 rxd1-skew-ps = <420>; /* 0ps */
87 rxd2-skew-ps = <420>; /* 0ps */
88 rxd3-skew-ps = <420>; /* 0ps */
89 txen-skew-ps = <0>; /* -420ps */
[all …]
Dsocfpga_arria5_socdk.dts65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txen-skew-ps = <0>;
70 txc-skew-ps = <2600>;
71 rxdv-skew-ps = <0>;
72 rxc-skew-ps = <2000>;
93 * because the LCD module does not work at the standard 100Khz
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { in smu10_set_soft_max_gfxclk_by_freq()
265 smu10_data->gfx_max_freq_limit = clock * 100; in smu10_set_soft_max_gfxclk_by_freq()
483 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; in smu10_get_clock_voltage_dependency_table()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
642 min_sclk /= 100; /* transfer 10KHz to MHz */ in smu10_dpm_force_dpm_level()
659 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
676 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
786 (data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) : in smu10_dpm_force_dpm_level()
792 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk / 100, in smu10_dpm_force_dpm_level()
[all …]

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