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/kernel/linux/linux-5.10/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
38 #define MDIO_CTRL2 7 /* 10G control 2 */
39 #define MDIO_STAT2 8 /* 10G status 2 */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
57 /* Media-dependent registers. */
58 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
38 #define MDIO_CTRL2 7 /* 10G control 2 */
39 #define MDIO_STAT2 8 /* 10G status 2 */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
Dfsl-ls2080a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "fsl-ls2080a.dtsi"
16 #include "fsl-ls208xa-rdb.dtsi"
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
24 stdout-path = "serial1:115200n8";
29 phy-handle = <&mdio2_phy1>;
30 phy-connection-type = "10gbase-r";
34 phy-handle = <&mdio2_phy2>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
22 * Adjustable tx de-emphasis (FFE)
31 The SERDES6G is a high-speed SERDES interface, which can operate at
34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_devids.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* Intel(R) Ethernet Connection E823-L for backplane */
10 /* Intel(R) Ethernet Connection E823-L for SFP */
12 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
14 /* Intel(R) Ethernet Connection E823-L 1GbE */
16 /* Intel(R) Ethernet Connection E823-L for QSFP */
18 /* Intel(R) Ethernet Controller E810-C for backplane */
20 /* Intel(R) Ethernet Controller E810-C for QSFP */
22 /* Intel(R) Ethernet Controller E810-C for SFP */
24 /* Intel(R) Ethernet Controller E810-XXV for backplane */
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/
Dice_devids.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
9 /* Intel(R) Ethernet Connection E823-L for backplane */
11 /* Intel(R) Ethernet Connection E823-L for SFP */
13 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
15 /* Intel(R) Ethernet Connection E823-L 1GbE */
17 /* Intel(R) Ethernet Connection E823-L for QSFP */
19 /* Intel(R) Ethernet Controller E830-C for backplane */
21 /* Intel(R) Ethernet Controller E830-C for QSFP */
23 /* Intel(R) Ethernet Controller E830-C for SFP */
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/microchip/
Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
36 gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>;
40 gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>;
53 default-state = "off";
58 default-state = "off";
60 led@10 {
[all …]
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-8040-mcbin-singleshot.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Single-shot";
12 compatible = "marvell,armada8040-mcbin-singleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
19 phy-mode = "10gbase-r";
20 managed = "in-band-status";
26 phy-mode = "10gbase-r";
27 managed = "in-band-status";
Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
Darmada-8040-mcbin-singleshot.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/leds/common.h>
10 #include "armada-8040-mcbin.dtsi"
13 model = "Marvell 8040 MACCHIATOBin Single-shot";
14 compatible = "marvell,armada8040-mcbin-singleshot",
15 "marvell,armada8040-mcbin", "marvell,armada8040",
16 "marvell,armada-ap806-quad", "marvell,armada-ap806";
19 compatible = "gpio-leds";
20 pinctrl-0 = <&cp0_led18_pins>;
21 pinctrl-names = "default";
[all …]
Dcn9130-crb.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
30 compatible = "regulator-gpio";
31 regulator-name = "ap0_mmc_vccq";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3300000>;
40 compatible = "regulator-fixed";
41 regulator-name = "cp0-xhci1-vbus";
42 regulator-min-microvolt = <5000000>;
[all …]
/kernel/linux/linux-6.6/Documentation/networking/
Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
144 * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/
Dserdes.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
46 /* 10GBASE-R and 10GBASE-X4/X2 */
61 /* 1000BASE-X and SGMII */
71 #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
83 #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
146 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
150 if (!chip->info->ops->serdes_get_lane) in mv88e6xxx_serdes_get_lane()
151 return -EOPNOTSUPP; in mv88e6xxx_serdes_get_lane()
153 return chip->info->ops->serdes_get_lane(chip, port); in mv88e6xxx_serdes_get_lane()
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/
Dserdes.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
42 /* 10GBASE-R and 10GBASE-X4/X2 */
46 /* 1000BASE-X and SGMII */
56 #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
68 #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
136 if (!chip->info->ops->serdes_get_lane) in mv88e6xxx_serdes_get_lane()
139 return chip->info->ops->serdes_get_lane(chip, port); in mv88e6xxx_serdes_get_lane()
145 if (!chip->info->ops->serdes_power) in mv88e6xxx_serdes_power_up()
146 return -EOPNOTSUPP; in mv88e6xxx_serdes_power_up()
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Dmarvell-88x2222.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver.
7 * 1000Base-X or 10GBase-R on the line side.
8 * SGMII over 1000Base-X.
38 /* 1000Base-X/SGMII Control Register */
41 /* 1000BASE-X/SGMII Status Register */
44 /* 1000Base-X Auto-Negotiation Advertisement Register */
47 /* 1000Base-X PHY Specific Status Register */
112 struct mv2222_data *priv = phydev->priv; in mv2222_set_sgmii_speed()
114 switch (phydev->speed) { in mv2222_set_sgmii_speed()
[all …]
/kernel/linux/linux-5.10/Documentation/networking/
Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces) insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
144 * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
[all …]

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