| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| D | allwinner,sun7i-a20-gmac-clk.yaml | 26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
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| D | allwinner,sun7i-a20-gmac-clk.yaml | 26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
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| /kernel/linux/linux-5.10/drivers/media/tuners/ |
| D | qt1010_priv.h | 22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
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| /kernel/linux/linux-6.6/drivers/media/tuners/ |
| D | qt1010_priv.h | 22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/ |
| D | ice_ptp_consts.h | 23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
26 823437500, /* 823.4375 MHz PLL */
33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
36 783360000, /* 783.36 MHz */
43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
46 796875000, /* 796.875 MHz */
53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
56 816000000, /* 816 MHz */
63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
66 830078125, /* 830.78125 MHz */
[all …]
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| /kernel/linux/linux-5.10/drivers/media/dvb-frontends/ |
| D | dvb-pll.c | 74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
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| /kernel/linux/linux-6.6/drivers/media/dvb-frontends/ |
| D | dvb-pll.c | 74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
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| /kernel/linux/linux-6.6/drivers/media/pci/cx18/ |
| D | cx18-firmware.c | 223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx18/ |
| D | cx18-firmware.c | 223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/spear/ |
| D | spear1340_clock.c | 164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/spear/ |
| D | spear1340_clock.c | 167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | qcom,dwc3.yaml | 44 - description: Master/Core clock, has to be >= 125 MHz
45 for SS operation and >= 60MHz for HS operation.
48 in host mode. Its frequency should be 19.2MHz.
67 - description: Must be 19.2MHz (19200000).
68 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
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| D | dwc3-xilinx.txt | 7 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
8 operation and >= 60MHz for HS operation
|
| /kernel/linux/linux-6.6/drivers/media/firewire/ |
| D | firedtv-fe.c | 173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
175 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
195 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
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| /kernel/linux/linux-5.10/drivers/media/firewire/ |
| D | firedtv-fe.c | 173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
175 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
195 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,ksz.yaml | 41 microchip,synclko-125:
44 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
50 microchip,synclko-125.
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-sti.c | 44 *| MII | n/a | 25Mhz |
47 *| GMII | 125Mhz | 25Mhz |
48 *| | clk-125/txclk | txclk |
50 *| RGMII | 125Mhz | 25Mhz |
51 *| | clk-125/txclk | clkgen |
54 *| RMII | n/a | 25Mhz |
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
| D | ksz.txt | 23 - microchip,synclko-125 : Set if the output SYNCLKO frequency should be set to
24 125MHz instead of 25MHz.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-sti.c | 45 *| MII | n/a | 25Mhz |
48 *| GMII | 125Mhz | 25Mhz |
49 *| | clk-125/txclk | txclk |
51 *| RGMII | 125Mhz | 25Mhz |
52 *| | clk-125/txclk | clkgen |
55 *| RMII | n/a | 25Mhz |
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
|