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/kernel/linux/linux-5.10/drivers/net/dsa/
Dmv88e6060.h17 #define PORT_STATUS_PAUSE_EN BIT(15)
18 #define PORT_STATUS_MY_PAUSE BIT(14)
20 #define PORT_STATUS_RESOLVED BIT(13)
21 #define PORT_STATUS_LINK BIT(12)
22 #define PORT_STATUS_PORTMODE BIT(11)
23 #define PORT_STATUS_PHYMODE BIT(10)
24 #define PORT_STATUS_DUPLEX BIT(9)
25 #define PORT_STATUS_SPEED BIT(8)
32 #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
33 #define PORT_CONTROL_TRAILER BIT(14)
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/
Dmv88e6060.h17 #define PORT_STATUS_PAUSE_EN BIT(15)
18 #define PORT_STATUS_MY_PAUSE BIT(14)
20 #define PORT_STATUS_RESOLVED BIT(13)
21 #define PORT_STATUS_LINK BIT(12)
22 #define PORT_STATUS_PORTMODE BIT(11)
23 #define PORT_STATUS_PHYMODE BIT(10)
24 #define PORT_STATUS_DUPLEX BIT(9)
25 #define PORT_STATUS_SPEED BIT(8)
32 #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
33 #define PORT_CONTROL_TRAILER BIT(14)
[all …]
/kernel/linux/linux-6.6/drivers/pmdomain/mediatek/
Dmt8195-pm-domains.h20 .sta_mask = BIT(11),
25 .sram_pdn_ack_bits = GENMASK(12, 12),
39 .sta_mask = BIT(12),
44 .sram_pdn_ack_bits = GENMASK(12, 12),
58 .sta_mask = BIT(13),
66 .sta_mask = BIT(14),
74 .sta_mask = BIT(18),
82 .sta_mask = BIT(3),
87 .sram_pdn_ack_bits = GENMASK(12, 12),
92 .sta_mask = BIT(10),
[all …]
Dmt8188-pm-domains.h20 .sta_mask = BIT(1),
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
30 .sta_mask = BIT(2),
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
66 .sta_mask = BIT(3),
70 .sram_pdn_bits = BIT(8),
71 .sram_pdn_ack_bits = BIT(12),
76 .sta_mask = BIT(4),
[all …]
Dmt8192-pm-domains.h16 .sta_mask = BIT(21),
21 .sram_pdn_ack_bits = GENMASK(12, 12),
55 .sta_mask = BIT(2),
60 .sram_pdn_ack_bits = GENMASK(12, 12),
65 .sta_mask = BIT(3),
70 .sram_pdn_ack_bits = GENMASK(12, 12),
93 .sta_mask = BIT(4),
98 .sram_pdn_ack_bits = GENMASK(12, 12),
102 .sta_mask = BIT(5),
107 .sram_pdn_ack_bits = GENMASK(12, 12),
[all …]
Dmt8186-pm-domains.h20 .sta_mask = BIT(2),
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
30 .sta_mask = BIT(3),
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
58 .sta_mask = BIT(4),
62 .sram_pdn_bits = BIT(8),
63 .sram_pdn_ack_bits = BIT(12),
68 .sta_mask = BIT(5),
[all …]
/kernel/linux/linux-6.6/include/soc/mscc/
Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
Docelot_ana.h11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/
Dmtk_dp_reg.h11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
26 #define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)
27 #define DA_CKM_XTAL_CK_FORCE_VAL BIT(9)
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
Docelot_ana.h11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
[all …]
/kernel/linux/linux-6.6/sound/firewire/bebob/
Dbebob_command.c16 buf = kzalloc(12, GFP_KERNEL); in avc_audio_set_selector()
30 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_set_selector()
31 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
32 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
54 buf = kzalloc(12, GFP_KERNEL); in avc_audio_get_selector()
68 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_get_selector()
69 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_get_selector()
70 BIT(6) | BIT(8)); in avc_audio_get_selector()
116 buf = kzalloc(12, GFP_KERNEL); in avc_bridgeco_get_plug_type()
123 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_bridgeco_get_plug_type()
[all …]
/kernel/linux/linux-6.6/drivers/staging/sm750fb/
Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
[all …]
/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
[all …]
/kernel/linux/linux-5.10/sound/firewire/bebob/
Dbebob_command.c16 buf = kzalloc(12, GFP_KERNEL); in avc_audio_set_selector()
30 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_set_selector()
31 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
32 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
54 buf = kzalloc(12, GFP_KERNEL); in avc_audio_get_selector()
68 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_get_selector()
69 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_get_selector()
70 BIT(6) | BIT(8)); in avc_audio_get_selector()
116 buf = kzalloc(12, GFP_KERNEL); in avc_bridgeco_get_plug_type()
123 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_bridgeco_get_plug_type()
[all …]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8186/
Dmt8186-reg.h12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
40 #define PDN_ADC_MASK_SFT BIT(24)
42 #define PDN_TDM_CK_MASK_SFT BIT(20)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Drtw8821c.c143 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
180 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
210 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
211 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); in rtw8821c_mac_init()
223 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
260 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
263 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
268 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
269 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
276 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
[all …]
/kernel/linux/linux-6.6/tools/arch/arm64/include/asm/
Dsysreg.h21 * [15-12] : CRn
29 #define CRn_shift 12
236 #define SYS_PAR_EL1_F BIT(0)
250 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
350 #define TRBLIMITR_LIMIT_SHIFT 12
351 #define TRBLIMITR_NVM BIT(5)
356 #define TRBLIMITR_ENABLE BIT(0)
360 #define TRBBASER_BASE_SHIFT 12
363 #define TRBSR_IRQ BIT(22)
364 #define TRBSR_TRG BIT(21)
[all …]
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Dsysreg.h21 * [15-12] : CRn
29 #define CRn_shift 12
238 #define SYS_PAR_EL1_F BIT(0)
252 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
348 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
349 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
351 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
352 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
353 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
354 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/
Drtw8821c.c74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tve200/
Dtve200_drm.h36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
43 #define TVE200_INT_Y_FIFO_UNDERRUN BIT(0)
49 #define TVE200_CTRL_YUV420 BIT(31)
50 #define TVE200_CTRL_CSMODE BIT(30)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/tve200/
Dtve200_drm.h36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
43 #define TVE200_INT_Y_FIFO_UNDERRUN BIT(0)
49 #define TVE200_CTRL_YUV420 BIT(31)
50 #define TVE200_CTRL_CSMODE BIT(30)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
[all …]

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