Searched +full:13 +full:- +full:bit (Results 1 – 25 of 1175) sorted by relevance
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| /kernel/linux/linux-6.6/drivers/net/ethernet/mediatek/ |
| D | mtk_ppe_regs.h | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
9 #define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
10 #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
11 #define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
12 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
13 #define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
14 #define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
15 #define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
16 #define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
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| /kernel/linux/linux-6.6/drivers/media/platform/samsung/exynos4-is/ |
| D | fimc-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
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| /kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/ |
| D | fimc-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
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| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/ |
| D | mt76_connac2_mac.h | 1 /* SPDX-License-Identifier: ISC */
39 #define MT_TX_FREE_STATUS GENMASK(14, 13)
41 #define MT_TX_FREE_PAIR BIT(31)
43 #define MT_TX_FREE_RATE GENMASK(13, 0)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
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| /kernel/linux/linux-6.6/include/soc/mscc/ |
| D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
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| /kernel/linux/linux-5.10/include/soc/mscc/ |
| D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
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| /kernel/linux/linux-6.6/include/linux/soc/mediatek/ |
| D | infracfg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
34 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
35 #define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
37 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
39 #define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
40 #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
42 #define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
43 #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
44 #define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
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| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | ni_tio_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
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| D | ni_stc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
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| /kernel/linux/linux-6.6/drivers/comedi/drivers/ |
| D | ni_tio_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
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| D | ni_stc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
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| /kernel/linux/linux-6.6/drivers/net/pcs/ |
| D | pcs-xpcs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define DW_VENDOR BIT(15)
16 #define DW_USXGMII_RST BIT(10)
17 #define DW_USXGMII_EN BIT(9)
19 #define DW_VR_RST BIT(15)
20 #define DW_EN_VSMMD1 BIT(13)
21 #define DW_CL37_BP BIT(12)
28 #define DW_USXGMII_FULL BIT(8)
29 #define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5))
30 #define DW_USXGMII_10000 (BIT(13) | BIT(6))
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| /kernel/linux/linux-6.6/drivers/net/ipa/reg/ |
| D | ipa_reg-v4.5.c | 1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
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| D | ipa_reg-v4.2.c | 1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
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| D | ipa_reg-v5.0.c | 1 // SPDX-License-Identifier: GPL-2.0
20 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
21 [GSI_SNOC_BYPASS_DIS] = BIT(1),
22 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
23 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
24 /* Bit 4 reserved */
25 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
26 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
27 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
28 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
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| D | ipa_reg-v4.11.c | 1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
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| D | ipa_reg-v4.9.c | 1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
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| D | ipa_reg-v4.7.c | 1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
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| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ |
| D | ia_css_ctc_types.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 * CSS-API header file for Chroma Tone Control parameters.
27 * IA_CSS_CTC_COEF_SHIFT(=13) includes not only the fractional bits
29 * from 13bit precision to 8bit precision.
32 * Input(Chorma) : s0.12 (13bit precision)
33 * Output(Chorma): s0.7 (8bit precision)
36 #define IA_CSS_CTC_COEF_SHIFT 13
41 #define IA_CSS_VAMEM_1_CTC_TABLE_SIZE BIT(IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2)
56 * (ISP1: CTC1 (CTC by look-up table) is used.)
61 u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
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| /kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/ |
| D | ia_css_ctc_types.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 * CSS-API header file for Chroma Tone Control parameters.
27 * IA_CSS_CTC_COEF_SHIFT(=13) includes not only the fractional bits
29 * from 13bit precision to 8bit precision.
32 * Input(Chorma) : s0.12 (13bit precision)
33 * Output(Chorma): s0.7 (8bit precision)
36 #define IA_CSS_CTC_COEF_SHIFT 13
41 #define IA_CSS_VAMEM_1_CTC_TABLE_SIZE BIT(IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2)
56 * (ISP1: CTC1 (CTC by look-up table) is used.)
61 u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
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| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| D | phy-mtk-hdmi-mt8195.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
34 #define RG_HDMITX21_VREF_SEL BIT(4)
35 #define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10)
37 #define RG_HDMITX21_BG_PWD BIT(20)
40 #define RG_HDMITX21_DRV_IMP_D0_EN1 GENMASK(13, 8)
46 #define RG_HDMITX21_CKLDO_EN BIT(3)
47 #define RG_HDMITX21_SLDOLPF_EN BIT(7)
51 #define RG_HDMITX21_D2_DRV_OP_EN BIT(8)
52 #define RG_HDMITX21_D1_DRV_OP_EN BIT(9)
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| /kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/ |
| D | mtk_dp_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | meson-mx-sdhc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | meson-mx-sdhc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
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