| /kernel/linux/linux-6.6/drivers/clk/spear/ |
| D | spear1340_clock.c | 21 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
28 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
48 #define SPEAR1340_SPDIF_CLK_MASK 1
53 #define SPEAR1340_GPT_CLK_MASK 1
61 #define SPEAR1340_C3_CLK_MASK 1
62 #define SPEAR1340_C3_CLK_SHIFT 1
65 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
83 #define SPEAR1340_I2S_REF_SEL_MASK 1
128 #define SPEAR1340_SYSROM_CLK_ENB 1
139 #define SPEAR1340_DDR_CORE_CLK_ENB 1
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/spear/ |
| D | spear1340_clock.c | 24 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
31 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
51 #define SPEAR1340_SPDIF_CLK_MASK 1
56 #define SPEAR1340_GPT_CLK_MASK 1
64 #define SPEAR1340_C3_CLK_MASK 1
65 #define SPEAR1340_C3_CLK_SHIFT 1
68 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
86 #define SPEAR1340_I2S_REF_SEL_MASK 1
131 #define SPEAR1340_SYSROM_CLK_ENB 1
142 #define SPEAR1340_DDR_CORE_CLK_ENB 1
[all …]
|
| /kernel/linux/linux-6.6/Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
64 # 7 chars 1 lines
[all …]
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| /kernel/linux/linux-5.10/Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
64 # 7 chars 1 lines
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-s3c2410.c | 57 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
61 { .val = 0, .div = 1 },
62 { .val = 1, .div = 2 },
74 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mvebu/ |
| D | mv98dx3236.c | 25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
98 {0, 1}, {3, 1}, {1, 1}, {1, 1},
99 {0, 1}, {1, 1}, {0, 1}, {0, 1},
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/mvebu/ |
| D | mv98dx3236.c | 25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
98 {0, 1}, {3, 1}, {1, 1}, {1, 1},
99 {0, 1}, {1, 1}, {0, 1}, {0, 1},
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | tsc_msr.c | 22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/kernel/ |
| D | tsc_msr.c | 22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | opp2xxx.h | 20 * 2430 (iva2.1, NOdsp, mdm)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define RB_CLKSEL_L3 (1 << 0)
104 #define RB_CLKSEL_L4 (1 << 5)
105 #define RB_CLKSEL_USB (1 << 25)
109 #define RB_CLKSEL_MPU (1 << 0)
111 #define RB_CLKSEL_DSP (1 << 0)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | opp2xxx.h | 20 * 2430 (iva2.1, NOdsp, mdm)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define RB_CLKSEL_L3 (1 << 0)
104 #define RB_CLKSEL_L4 (1 << 5)
105 #define RB_CLKSEL_USB (1 << 25)
109 #define RB_CLKSEL_MPU (1 << 0)
111 #define RB_CLKSEL_DSP (1 << 0)
112 #define RB_CLKSEL_DSP_IF (1 << 5)
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/vt6655/ |
| D | rf.c | 57 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
58 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
59 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
60 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
61 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
62 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
63 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
64 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
65 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
66 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_mipi_dsi.c | 31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
|
| /kernel/linux/linux-6.6/arch/mips/txx9/rbtx4927/ |
| D | setup.c | 75 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
93 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
122 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
140 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
164 gpio_direction_output(15, 1); in rbtx4927_gpio_init()
190 writeb(1, rbtx4927_softresetlock_addr); in toshiba_rbtx4927_restart()
193 while (!(readb(rbtx4927_softresetlock_addr) & 1)) in toshiba_rbtx4927_restart()
197 writeb(1, rbtx4927_softreset_addr); in toshiba_rbtx4927_restart()
231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
234 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). in rbtx4927_clock_init()
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/txx9/rbtx4927/ |
| D | setup.c | 75 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
93 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
122 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
140 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
164 gpio_direction_output(15, 1); in rbtx4927_gpio_init()
190 writeb(1, rbtx4927_softresetlock_addr); in toshiba_rbtx4927_restart()
193 while (!(readb(rbtx4927_softresetlock_addr) & 1)) in toshiba_rbtx4927_restart()
197 writeb(1, rbtx4927_softreset_addr); in toshiba_rbtx4927_restart()
231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
234 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). in rbtx4927_clock_init()
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/usb/dvb-usb-v2/ |
| D | af9035.h | 56 u8 dual_mode:1;
57 u8 no_read:1;
75 { 0x67, 0x63, 1 },
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/usb/dvb-usb-v2/ |
| D | af9035.h | 56 u8 dual_mode:1;
57 u8 no_read:1;
75 { 0x67, 0x63, 1 },
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/tuners/ |
| D | tuner-types.c | 65 { 16 * 140.25 /*MHz*/, 0x8e, 0x02, },
66 { 16 * 463.25 /*MHz*/, 0x8e, 0x04, },
81 { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, },
82 { 16 * 463.25 /*MHz*/, 0x8e, 0x90, },
97 { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, },
98 { 16 * 451.25 /*MHz*/, 0x8e, 0x90, },
107 .cb_first_if_lower_freq = 1,
114 { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, },
115 { 16 * 447.25 /*MHz*/, 0x8e, 0x97, },
124 .cb_first_if_lower_freq = 1,
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/tuners/ |
| D | tuner-types.c | 65 { 16 * 140.25 /*MHz*/, 0x8e, 0x02, },
66 { 16 * 463.25 /*MHz*/, 0x8e, 0x04, },
81 { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, },
82 { 16 * 463.25 /*MHz*/, 0x8e, 0x90, },
97 { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, },
98 { 16 * 451.25 /*MHz*/, 0x8e, 0x90, },
107 .cb_first_if_lower_freq = 1,
114 { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, },
115 { 16 * 447.25 /*MHz*/, 0x8e, 0x97, },
124 .cb_first_if_lower_freq = 1,
[all …]
|
| /kernel/linux/linux-5.10/Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 10 :header-rows: 1
14 - .. row 1
30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
[all …]
|
| /kernel/linux/linux-6.6/Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 10 :header-rows: 1
14 - .. row 1
30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
36 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu11_driver_if_vangogh.h | 45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
62 #define WM_RETRAINING 1
124 //Freq in MHz
156 #define THROTTLER_STATUS_BIT_FPPT 1
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
170 uint16_t VclkFrequency; //[MHz]
171 uint16_t DclkFrequency; //[MHz]
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpu/ |
| D | cpu-capacity.txt | 6 1 - Introduction
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
[all …]
|