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Searched +full:1 +full:qav (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,k3-am654-cpsw-nuss.yaml21 One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
30 Support for Audio/Video Bridging (P802.1Qav/D6.0)
56 maxItems: 1
76 maxItems: 1
97 const: 1
102 port@1:
111 - const: 1
115 maxItems: 1
206 #address-cells = <1>;
209 cpsw_port1: port@1 {
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dti,k3-am654-cpsw-nuss.yaml27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
65 maxItems: 1
78 maxItems: 1
90 maxItems: 1
111 const: 1
116 "^port@[1-8]$":
125 minimum: 1
130 minItems: 1
138 minItems: 1
209 "^port@[1-4]$":
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/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/intel/
Digb.rst51 also force the VMDq parameter to be 1 or more.
181 Credit Based Shaper (Qav Mode)
/kernel/linux/linux-6.6/Documentation/networking/device_drivers/ethernet/intel/
Digb.rst51 also force the VMDq parameter to be 1 or more.
181 Credit Based Shaper (Qav Mode)
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igb/
De1000_defines.h181 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
189 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
196 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
220 #define E1000_PCS_LCTL_FLV_LINK_UP 1
232 #define E1000_PCS_LSTS_LINK_OK 1
239 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
240 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
243 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
260 #define HALF_DUPLEX 1
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Digb_main.c240 static int debug = -1;
347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], in igb_regdump()
454 16, 1, buffer_info->skb->data, in igb_dump()
477 * 63 1 0 in igb_dump()
479 * 0 | Packet Buffer Address [63:1] |A0/NSE| in igb_dump()
481 * 8 | Header Buffer Address [63:1] | DD | in igb_dump()
539 16, 1, in igb_dump()
570 * @state: I2C data value (0 or 1) to set
690 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. in igb_cache_ring_register()
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/kernel/linux/linux-6.6/drivers/net/ethernet/intel/igb/
De1000_defines.h181 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
189 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
196 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
220 #define E1000_PCS_LCTL_FLV_LINK_UP 1
232 #define E1000_PCS_LSTS_LINK_OK 1
239 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
240 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
243 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
260 #define HALF_DUPLEX 1
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Digb_main.c241 static int debug = -1;
348 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], in igb_regdump()
455 16, 1, buffer_info->skb->data, in igb_dump()
478 * 63 1 0 in igb_dump()
480 * 0 | Packet Buffer Address [63:1] |A0/NSE| in igb_dump()
482 * 8 | Header Buffer Address [63:1] | DD | in igb_dump()
540 16, 1, in igb_dump()
571 * @state: I2C data value (0 or 1) to set
693 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
709 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. in igb_cache_ring_register()
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/
D0008_linux_net.patch52 - buf[1] = '\n';
167 + if (1 == num) {
204 + atomic_set(&shinfo->dataref, 1);
245 + macaddr[i] = mac[ETH_ALEN - i - 1];
471 refcount_set(&sch->refcnt, 1);
531 - WARN_ON_ONCE(1);
552 @@ -0,0 +1,15 @@
560 + 802.1Qav:
573 @@ -0,0 +1 @@
580 @@ -0,0 +1,3730 @@
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D0005_linux_include.patch14 @@ -0,0 +1,921 @@
315 +#define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1)
318 +#define SOURCE_PHY_RSTN_EN BIT(1)
323 +#define SOURCE_PKT_DATA_RSTN_EN BIT(1)
330 +#define SOURCE_AIF_CLK_RSTN_EN BIT(1)
335 +#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1)
338 +#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1)
342 +#define APB_DRAM_PATH BIT(1)
345 +#define MAILBOX_INT_MASK_BIT BIT(1)
351 +#define MB_MODULE_ID 1
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