| /kernel/linux/linux-5.10/tools/testing/selftests/powerpc/math/ |
| D | vmx_asm.S | 9 # Should be safe from C, only touches r4, r5 and v0,v1,v2
13 li r3,1 # assume a bad result
17 vmr v2,v1
22 vand v2,v2,v1
27 vand v2,v2,v1
32 vand v2,v2,v1
37 vand v2,v2,v1
42 vand v2,v2,v1
47 vand v2,v2,v1
52 vand v2,v2,v1
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/powerpc/math/ |
| D | vmx_asm.S | 9 # Should be safe from C, only touches r4, r5 and v0,v1,v2
13 li r3,1 # assume a bad result
17 vmr v2,v1
22 vand v2,v2,v1
27 vand v2,v2,v1
32 vand v2,v2,v1
37 vand v2,v2,v1
42 vand v2,v2,v1
47 vand v2,v2,v1
52 vand v2,v2,v1
[all …]
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| /kernel/linux/linux-6.6/net/ceph/ |
| D | messenger_v2.c | 30 #define FRAME_TAG_HELLO 1
55 #define IN_S_HANDLE_PREAMBLE 1
66 #define OUT_S_QUEUE_DATA 1
98 return 1; in do_recvmsg()
105 * 1 - done, nothing (else) to read
114 iov_iter_is_discard(&con->v2.in_iter) ? "discard" : "need", in ceph_tcp_recv()
115 iov_iter_count(&con->v2.in_iter)); in ceph_tcp_recv()
116 ret = do_recvmsg(con->sock, &con->v2.in_iter); in ceph_tcp_recv()
118 iov_iter_count(&con->v2.in_iter)); in ceph_tcp_recv()
140 return 1; in do_sendmsg()
[all …]
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| /kernel/linux/linux-6.6/arch/s390/include/asm/ |
| D | vx-insn-asm.h | 34 \opd = 1
98 \opd = 1
100 .ifc \vxr,%v2
199 * @v2: Second vector register designated operand
203 .macro RXB rxb v1 v2=0 v3=0 v4=0
208 .if \v2 & 0x10
223 * @v2: Second vector register designated operand (for RXB)
227 .macro MRXB m v1 v2=0 v3=0 v4=0
229 RXB rxb, \v1, \v2, \v3, \v4
238 * @v2: Second vector register designated operand (for RXB)
[all …]
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| /kernel/linux/linux-6.6/include/uapi/linux/ |
| D | nfs.h | 22 #define NFS_FIFO_DEV (-1)
33 #define NFS_MNT_VERSION 1
43 * Error codes that have a `--' in the v2 column are not part of the
47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
[all …]
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| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | nfs.h | 22 #define NFS_FIFO_DEV (-1)
33 #define NFS_MNT_VERSION 1
43 * Error codes that have a `--' in the v2 column are not part of the
47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
[all …]
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| /kernel/linux/linux-5.10/arch/s390/crypto/ |
| D | crc32le-vx.S | 38 * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
39 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
40 * R3 = [(x128+32 mod P'(x) << 32)]' << 1
41 * R4 = [(x128-32 mod P'(x) << 32)]' << 1
42 * R5 = [(x64 mod P'(x) << 32)]' << 1
43 * R6 = [(x32 mod P'(x) << 32)]' << 1
68 .octa 0x1DB710641 # P'(x) << 1
76 .octa 0x105ec76f0 # P'(x) << 1
132 VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
156 * in V2, V3, and V4 respectively.
[all …]
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| D | crc32be-vx.S | 52 * can be multiplied by 1 to perform an XOR without the need for a separate
64 .quad 0x0f200aa66, 1 << 32 # R5, x32
65 .quad 0x0490d678d, 1 # R6, 1
121 * in V2, V3, and V4 respectively.
124 VGFMAG %v2,CONST_R1R2,%v2,%v6
137 VGFMAG %v1,CONST_R3R4,%v1,%v2
147 VL %v2,0,,%r3 /* Load next data chunk */
148 VGFMAG %v1,CONST_R3R4,%v1,%v2 /* Fold next data chunk */
162 * VGFMG instruction, multiply the rightmost 64-bit with x^32 (1<<32) to
185 * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
[all …]
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| /kernel/linux/linux-6.6/arch/s390/crypto/ |
| D | crc32le-vx.S | 38 * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
39 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
40 * R3 = [(x128+32 mod P'(x) << 32)]' << 1
41 * R4 = [(x128-32 mod P'(x) << 32)]' << 1
42 * R5 = [(x64 mod P'(x) << 32)]' << 1
43 * R6 = [(x32 mod P'(x) << 32)]' << 1
68 .octa 0x1DB710641 # P'(x) << 1
77 .octa 0x105ec76f0 # P'(x) << 1
134 VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
158 * in V2, V3, and V4 respectively.
[all …]
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| D | crc32be-vx.S | 52 * can be multiplied by 1 to perform an XOR without the need for a separate
64 .quad 0x0f200aa66, 1 << 32 # R5, x32
65 .quad 0x0490d678d, 1 # R6, 1
122 * in V2, V3, and V4 respectively.
125 VGFMAG %v2,CONST_R1R2,%v2,%v6
138 VGFMAG %v1,CONST_R3R4,%v1,%v2
148 VL %v2,0,,%r3 /* Load next data chunk */
149 VGFMAG %v1,CONST_R3R4,%v1,%v2 /* Fold next data chunk */
163 * VGFMG instruction, multiply the rightmost 64-bit with x^32 (1<<32) to
186 * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
[all …]
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| /kernel/linux/linux-5.10/arch/s390/include/asm/ |
| D | vx-insn.h | 31 \opd = 1
95 \opd = 1
97 .ifc \vxr,%v2
196 * @v2: Second vector register designated operand
200 .macro RXB rxb v1 v2=0 v3=0 v4=0
205 .if \v2 & 0x10
220 * @v2: Second vector register designated operand (for RXB)
224 .macro MRXB m v1 v2=0 v3=0 v4=0
226 RXB rxb, \v1, \v2, \v3, \v4
235 * @v2: Second vector register designated operand (for RXB)
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
39 operating-points-v2 = <&cpu0_opp_table0>;
42 cpu@1 {
45 reg = <1>;
50 operating-points-v2 = <&cpu0_opp_table0>;
55 compatible = "operating-points-v2";
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,spm.yaml | 21 - qcom,sdm660-gold-saw2-v4.1-l2
22 - qcom,sdm660-silver-saw2-v4.1-l2
23 - qcom,msm8998-gold-saw2-v4.1-l2
24 - qcom,msm8998-silver-saw2-v4.1-l2
28 - qcom,msm8226-saw2-v2.1-cpu
29 - qcom,msm8974-saw2-v2.1-cpu
30 - qcom,msm8976-gold-saw2-v2.3-l2
31 - qcom,msm8976-silver-saw2-v2.3-l2
32 - qcom,apq8084-saw2-v2.1-cpu
33 - qcom,apq8064-saw2-v1.1-cpu
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
108 - qcom,msm8996-smmu-v2
109 - qcom,sc7180-smmu-v2
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/rtl8188eu/hal/ |
| D | rf_cfg.c | 143 #define READ_NEXT_PAIR(v1, v2, i) \ argument
146 v2 = array[i + 1]; \
161 mdelay(1); in rtl_rfreg_delay()
167 udelay(1); in rtl_rfreg_delay()
170 udelay(1); in rtl_rfreg_delay()
192 u32 v2 = array[i + 1]; in rtl88e_phy_config_rf_with_headerfile() local
195 rtl8188e_config_rf_reg(adapt, v1, v2); in rtl88e_phy_config_rf_with_headerfile()
199 READ_NEXT_PAIR(v1, v2, i); in rtl88e_phy_config_rf_with_headerfile()
200 while (v2 != 0xDEAD && v2 != 0xCDEF && in rtl88e_phy_config_rf_with_headerfile()
201 v2 != 0xCDCD && i < array_len - 2) in rtl88e_phy_config_rf_with_headerfile()
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/crypto/ |
| D | sm4-ce-core.S | 17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
63 sm4ekey v2.4s, v1.4s, v26.4s;
64 sm4ekey v3.4s, v2.4s, v27.4s;
81 tbl v21.16b, {v2.16b}, v24.16b
124 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7);
140 SM4_CRYPT_BLK4(v0, v1, v2, v3);
146 sub w3, w3, #1;
183 eor v2.16b, v2.16b, v1.16b
184 SM4_CRYPT_BLK(v2)
185 eor v3.16b, v3.16b, v2.16b
[all …]
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| D | aes-modes.S | 26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
76 subs w4, w4, #1
106 subs w4, w4, #1
148 eor v2.16b, v2.16b, v1.16b
149 encrypt_block v2, w3, x2, x6, w7
150 eor v3.16b, v3.16b, v2.16b
163 subs w4, w4, #1
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/lib/ |
| D | xor_vmx.c | 31 V##_1 = V[1]; \
39 V[1] = V##_1; \
44 #define XOR(V1, V2) \ argument
46 V1##_0 = vec_xor(V1##_0, V2##_0); \
47 V1##_1 = vec_xor(V1##_1, V2##_1); \
48 V1##_2 = vec_xor(V1##_2, V2##_2); \
49 V1##_3 = vec_xor(V1##_3, V2##_3); \
57 DEFINE(v2); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
63 XOR(v1, v2); in __xor_altivec_2()
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/lib/ |
| D | xor_vmx.c | 31 V##_1 = V[1]; \
39 V[1] = V##_1; \
44 #define XOR(V1, V2) \ argument
46 V1##_0 = vec_xor(V1##_0, V2##_0); \
47 V1##_1 = vec_xor(V1##_1, V2##_1); \
48 V1##_2 = vec_xor(V1##_2, V2##_2); \
49 V1##_3 = vec_xor(V1##_3, V2##_3); \
56 DEFINE(v2); in __xor_altivec_2()
61 LOAD(v2); in __xor_altivec_2()
62 XOR(v1, v2); in __xor_altivec_2()
[all …]
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| /kernel/linux/linux-6.6/Documentation/powerpc/ |
| D | isa-versions.rst | 12 Power10 Power ISA v3.1
14 Power8 Power ISA v2.07
15 e6500 Power ISA v2.06 with some exceptions
16 e5500 Power ISA v2.06 with some exceptions, no Altivec
17 Power7 Power ISA v2.06
18 Power6 Power ISA v2.05
19 PA6T Power ISA v2.04
20 Cell PPU - Power ISA v2.02 with some minor exceptions
22 Power5++ Power ISA v2.04 (no VMX)
23 Power5+ Power ISA v2.03
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/crypto/ |
| D | aes-modes.S | 26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
77 subs w4, w4, #1
108 subs w4, w4, #1
150 eor v2.16b, v2.16b, v1.16b
151 encrypt_block v2, w3, x2, x6, w7
152 eor v3.16b, v3.16b, v2.16b
165 subs w4, w4, #1
[all …]
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| D | sm3-ce-core.S | 11 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
45 shl \t1\().4s, \t0\().4s, #1
62 round \ab, \s0, v12, v11, 1
89 sub w2, w2, #1
96 CPU_LE( rev32 v2.16b, v2.16b )
101 qround a, v0, v1, v2, v3, v4
102 qround a, v1, v2, v3, v4, v0
103 qround a, v2, v3, v4, v0, v1
104 qround a, v3, v4, v0, v1, v2
108 qround b, v4, v0, v1, v2, v3
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | fsl-fman.txt | 44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
50 DCFG_DEVDISR2[14] 2 1
56 DCFG_CCSR_DEVDISR2[24] 1 0
57 DCFG_CCSR_DEVDISR2[25] 2 1
170 - "fsl,fman-v2-port-oh" for FManV2 OH ports
171 - "fsl,fman-v2-port-rx" for FManV2 RX ports
172 - "fsl,fman-v2-port-tx" for FManV2 TX ports
202 Definition: The default port rate is 1G.
216 compatible = "fsl,fman-v2-port-tx";
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | fsl-fman.txt | 44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
50 DCFG_DEVDISR2[14] 2 1
56 DCFG_CCSR_DEVDISR2[24] 1 0
57 DCFG_CCSR_DEVDISR2[25] 2 1
170 - "fsl,fman-v2-port-oh" for FManV2 OH ports
171 - "fsl,fman-v2-port-rx" for FManV2 RX ports
172 - "fsl,fman-v2-port-tx" for FManV2 TX ports
202 Definition: The default port rate is 1G.
216 compatible = "fsl,fman-v2-port-tx";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sc7180-smmu-v2
32 - qcom,sdm845-smmu-v2
33 - const: qcom,smmu-v2
54 - const: arm,smmu-v2
62 - arm,smmu-v2
66 - cavium,smmu-v2
[all …]
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