Searched +full:1 +full:e000000 (Results 1 – 25 of 99) sorted by relevance
1234
18 maxItems: 133 ccplex@e000000 {
16 flash@1e000000 {23 #address-cells = <1>;24 #size-cells = <1>;
15 in bytes. Must be 1 or 2.23 - #address-cells: should be set to 124 - #size-cells: should be set to 128 gpmc: gpmc@6e000000 {36 #size-cells = <1>;43 #address-cells = <1>;44 #size-cells = <1>;
26 nand-controller@4e000000 {30 #address-cells = <1>;42 #address-cells = <1>;43 #size-cells = <1>;
12 16-bit devices and so must be either 1 or 2 bytes.34 - #address-cells: should be set to 135 - #size-cells: should be set to 139 gpmc: gpmc@6e000000 {47 #size-cells = <1>;54 #address-cells = <1>;55 #size-cells = <1>;
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox15 #mbox-cells = <1>;36 mboxes = <&mailbox 0 &mailbox 1>;45 #address-cells = <1>;46 #size-cells = <1>;55 client@2e000000 {
57 maxItems: 167 maxItems: 175 Set to 1 in data transfer mode and represents index of the channel.78 enum: [ 1, 2 ]96 #mbox-cells = <1>;102 clocks = <&clock 0 2 1>;106 mhu_client_scb: scb@2e000000 {109 mboxes = <&mhuA 1>; /* HP-NonSecure */126 clocks = <&clock 0 2 1>;133 mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */
54 gpmc: memory-controller@6e000000 {63 #size-cells = <1>;66 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */71 #address-cells = <1>;72 #size-cells = <1>;
26 reg = <0x80000000 0x40000000>; /* 1 GB */29 uart@3e000000 {
14 #address-cells = <1>;15 #size-cells = <1>;63 #address-cells = <1>;66 phy0: ethernet-phy@1 {67 reg = <1>;111 gpio1: gpio@4e000000 {123 ethernet-port@1 {
29 maxItems: 146 ccplex@e000000 {
22 const: 125 const: 131 maxItems: 142 maxItems: 160 palmbus@1e000000 {63 #address-cells = <1>;64 #size-cells = <1>;
22 palmbus: palmbus@1e000000 {47 #address-cells = <1>;48 #size-cells = <1>;96 gmac1: mac@1 {
22 palmbus: palmbus@1E000000 {63 #address-cells = <1>;64 #size-cells = <1>;97 /* This is normally 1/4 of cpuclock */
5 #address-cells = <1>;6 #size-cells = <1>;14 cpu@1 {21 #interrupt-cells = <1>;42 /* This is normally 1/4 of cpuclock */61 mmc_fixed_1v8_io: fixedregulator@1 {70 palmbus: palmbus@1E000000 {75 #address-cells = <1>;76 #size-cells = <1>;108 #address-cells = <1>;[all …]
12 #address-cells = <1>;13 #size-cells = <1>;20 #interrupt-cells = <1>;23 gic: interrupt-controller@1bdc0000 {40 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;48 #interrupt-cells = <1>;54 flash@1e000000 {58 #address-cells = <1>;59 #size-cells = <1>;63 #address-cells = <1>;[all …]
20 #address-cells = <1>;21 #size-cells = <1>;40 #interrupt-cells = <1>;45 * to uplink only 1 IRQ to ARC core intc50 #address-cells = <1>;95 #interrupt-cells = <1>;120 frame_buffer: frame_buffer@9e000000 {
45 - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or71 rb: rb@7e000000 {