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/kernel/linux/linux-6.6/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
64 # 7 chars 1 lines
[all …]
/kernel/linux/linux-5.10/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
64 # 7 chars 1 lines
[all …]
/kernel/linux/linux-6.6/include/sound/
Dasoundef.h17 #define IEC958_AES0_PROFESSIONAL (1<<0) /* 0 = consumer, 1 = professional */
18 #define IEC958_AES0_NONAUDIO (1<<1) /* 0 = audio, 1 = non-audio */
21 #define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */
24 #define IEC958_AES0_PRO_FREQ_UNLOCKED (1<<5) /* source sample frequency: 0 = locked, 1 = unlocked */
27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
30 #define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
33 #define IEC958_AES0_CON_EMPHASIS_5015 (1<<3) /* 50/15us emphasis */
98 #define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */
[all …]
Demu10k1.h62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
89 /* Clear pending interrupts by writing a 1 to */
186 /* NOTE: Each channel takes 1/64th of a sample */
203 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
204 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
205 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
224 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
247 /* 1 = Force all 3 async digital inputs to use */
[all …]
Ddesignware_i2s.h16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
27 #define DWC_I2S_PLAY (1 << 0)
28 #define DWC_I2S_RECORD (1 << 1)
29 #define DW_I2S_SLAVE (1 << 2)
30 #define DW_I2S_MASTER (1 << 3)
36 #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
37 #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
38 #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
/kernel/linux/linux-5.10/include/sound/
Dasoundef.h17 #define IEC958_AES0_PROFESSIONAL (1<<0) /* 0 = consumer, 1 = professional */
18 #define IEC958_AES0_NONAUDIO (1<<1) /* 0 = audio, 1 = non-audio */
21 #define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */
24 #define IEC958_AES0_PRO_FREQ_UNLOCKED (1<<5) /* source sample frequency: 0 = locked, 1 = unlocked */
27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
30 #define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
33 #define IEC958_AES0_CON_EMPHASIS_5015 (1<<3) /* 50/15us emphasis */
98 #define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */
[all …]
Demu10k1.h65 /* Clear pending interrupts by writing a 1 to */
155 /* NOTE: Each channel takes 1/64th of a sample */
172 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
173 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
174 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
178 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
179 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
192 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
216 /* 1 = Force all 3 async digital inputs to use */
219 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
[all …]
Ddesignware_i2s.h16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
25 #define DWC_I2S_PLAY (1 << 0)
26 #define DWC_I2S_RECORD (1 << 1)
27 #define DW_I2S_SLAVE (1 << 2)
28 #define DW_I2S_MASTER (1 << 3)
34 #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
35 #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
36 #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
/kernel/linux/linux-5.10/sound/ppc/
Dawacs.h25 unsigned byteswap; /* Data is little-endian if 1 */
45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
56 #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
91 /* Address 1 Bit Masks */
98 #define MASK_CMUTE (0x1 << 7) /* Output C (Speaker) Mute when 1 */
102 #define MASK_AMUTE (0x1 << 9) /* Output A (Headphone) Mute when 1 */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
[all …]
/kernel/linux/linux-6.6/sound/ppc/
Dawacs.h25 unsigned byteswap; /* Data is little-endian if 1 */
45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
56 #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
91 /* Address 1 Bit Masks */
98 #define MASK_CMUTE (0x1 << 7) /* Output C (Speaker) Mute when 1 */
102 #define MASK_AMUTE (0x1 << 9) /* Output A (Headphone) Mute when 1 */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h44 PANEL_6BIT_COLOR = 1,
67 uint32_t enum_id:16; /* 1 based enum */
110 uint32_t HORIZONTAL_CUT_OFF:1;
111 /* 0=Active High, 1=Active Low */
112 uint32_t H_SYNC_POLARITY:1;
113 /* 0=Active High, 1=Active Low */
114 uint32_t V_SYNC_POLARITY:1;
115 uint32_t VERTICAL_CUT_OFF:1;
116 uint32_t H_REPLICATION_BY2:1;
117 uint32_t V_REPLICATION_BY2:1;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h44 PANEL_6BIT_COLOR = 1,
67 uint32_t enum_id:16; /* 1 based enum */
110 uint32_t HORIZONTAL_CUT_OFF:1;
111 /* 0=Active High, 1=Active Low */
112 uint32_t H_SYNC_POLARITY:1;
113 /* 0=Active High, 1=Active Low */
114 uint32_t V_SYNC_POLARITY:1;
115 uint32_t VERTICAL_CUT_OFF:1;
116 uint32_t H_REPLICATION_BY2:1;
117 uint32_t V_REPLICATION_BY2:1;
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
47 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
63 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
47 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
63 { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
19 Shall have value <1>.
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
40 #clock-cells = <1>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherials to enable low
19 Shall have value <1>.
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
40 #clock-cells = <1>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-ivi-audio.yaml21 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
23 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
28 Clocking setup for 48KHz family:
35 Clocking setup for 44.1KHz family:
74 - description: Parent for CPB_McASP auxclk (for 48KHz)
75 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
77 - description: Parent for CPB_SCKI clock (for 48KHz)
78 - description: Parent for CPB_SCKI clock (for 44.1KHz)
80 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
Dti,j721e-cpb-audio.yaml16 In order to support 48KHz and 44.1KHz family of sampling rates the parent
17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
18 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
22 48KHz family:
26 44.1KHz family:
31 48KHz family:
84 - description: Parent for CPB_McASP auxclk (for 48KHz)
85 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
87 - description: Parent for CPB_SCKI clock (for 48KHz)
88 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
/kernel/linux/linux-5.10/Documentation/sound/cards/
Daudiophile-usb.rst35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
125 way (I suppose the device's index is 1):
127 * hw:1,0 is Ao in playback and Di in capture
128 * hw:1,1 is Do in playback and Ai in capture
129 * hw:1,2 is Do in AC3/DTS passthrough mode
[all …]
/kernel/linux/linux-6.6/Documentation/sound/cards/
Daudiophile-usb.rst35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
125 way (I suppose the device's index is 1):
127 * hw:1,0 is Ao in playback and Di in capture
128 * hw:1,1 is Do in playback and Ai in capture
129 * hw:1,2 is Do in AC3/DTS passthrough mode
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/alsa/
Dpcm-test.conf2 description "8kHz mono large periods"
6 channels 1
11 description "8kHz stereo large periods"
20 description "44.1kHz stereo large periods"
29 description "48kHz stereo small periods"
38 description "48kHz stereo large periods"
47 description "48kHz 6 channel large periods"
56 description "96kHz stereo large periods"
/kernel/linux/linux-6.6/sound/pci/ca0106/
Dca0106.h65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
[all …]
/kernel/linux/linux-5.10/sound/pci/ca0106/
Dca0106.h65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
[all …]

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