| /kernel/linux/linux-5.10/arch/arm64/crypto/ |
| D | sha3-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
16 .set .Lv\b\().2d, \b
21 * ARMv8.2 Crypto Extensions instructions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/crypto/ |
| D | sha3-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
16 .set .Lv\b\().2d, \b
21 * ARMv8.2 Crypto Extensions instructions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
[all …]
|
| /kernel/linux/linux-5.10/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
72 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
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| /kernel/linux/linux-6.6/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
72 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
33 * Component 2: B
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
33 * Component 2: B
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/ |
| D | mdp_format.c | 1 // SPDX-License-Identifier: GPL-2.0-only
87 FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
89 FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
91 FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
93 FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
95 FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
97 FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
99 FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
101 FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
103 FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/ |
| D | mdp_format.c | 1 // SPDX-License-Identifier: GPL-2.0-only
89 FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
91 FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
93 FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
95 FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
97 FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
99 FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
101 FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
103 FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
105 FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
[all …]
|
| /kernel/linux/linux-5.10/arch/xtensa/variants/test_kc705_be/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
72 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
|
| /kernel/linux/linux-6.6/arch/xtensa/variants/test_kc705_be/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
72 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/test-drivers/vicodec/ |
| D | codec-fwht.c | 1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
21 * be guaranteed that the magic 8 byte sequence (see below) can
34 1, 8,
35 2, 9, 16,
57 s16 block[8 * 8]; in rlc()
67 for (y = 0; y < 8; y++) { in rlc()
68 for (x = 0; x < 8; x++) { in rlc()
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/test-drivers/vicodec/ |
| D | codec-fwht.c | 1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
14 #include "codec-fwht.h"
20 * be guaranteed that the magic 8 byte sequence (see below) can
33 1, 8,
34 2, 9, 16,
56 s16 block[8 * 8]; in rlc()
66 for (y = 0; y < 8; y++) { in rlc()
67 for (x = 0; x < 8; x++) { in rlc()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/display/ |
| D | drm_dsc_helper.c | 1 // SPDX-License-Identifier: MIT
34 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
48 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
49 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
54 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
56 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
81 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
109 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
110 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-davinci/ |
| D | da830.c | 7 * the terms of the GNU General Public License version 2. This program
11 #include <linux/clk-provider.h>
16 #include <linux/irqchip/irq-davinci-cp-intc.h>
17 #include <linux/platform_data/gpio-davinci.h>
25 #include <clocksource/timer-davinci.h>
30 /* Offsets of the 8 compare registers on the da830 */
51 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
53 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
54 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
56 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-davinci/ |
| D | da830.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
26 /* Offsets of the 8 compare registers on the da830 */
47 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
49 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
50 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
52 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
59 MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false)
[all …]
|
| /kernel/linux/linux-6.6/include/sound/ |
| D | ump_msg.h | 1 // SPDX-License-Identifier: GPL-2.0-or-later
31 UMP_CC_BREATH = 2,
36 UMP_CC_BALANCE = 8,
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
154 u32 note:8;
155 u32 data:8;
157 u32 data:8;
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-omap1/ |
| D | opp_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/opp_data.c
5 * Copyright (C) 2004 - 2005 Nokia corporation
13 /*-------------------------------------------------------------------------
15 *-------------------------------------------------------------------------*/
21 { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
23 { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
25 { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
27 { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
29 { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| D | opp_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/opp_data.c
5 * Copyright (C) 2004 - 2005 Nokia corporation
13 /*-------------------------------------------------------------------------
15 *-------------------------------------------------------------------------*/
21 { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
23 { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
25 { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
27 { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
29 { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
[all …]
|
| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-generic/xor.h
5 * Generic optimized RAID-5 checksumming functions.
13 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_2()
18 p1[2] ^= p2[2]; in xor_8regs_2()
24 p1 += 8; in xor_8regs_2()
25 p2 += 8; in xor_8regs_2()
26 } while (--lines > 0); in xor_8regs_2()
33 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_3()
38 p1[2] ^= p2[2] ^ p3[2]; in xor_8regs_3()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt8173.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt8173.h"
22 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
24 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
25 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
27 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt8173.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "pinctrl-mtk-common.h"
16 #include "pinctrl-mtk-mt8173.h"
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
[all …]
|
| /kernel/linux/linux-6.6/arch/arc/include/asm/ |
| D | arcregs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
63 * ECR: Exception Cause Reg bits-n-pieces
65 * [15: 8] = Exception Cause Code
101 #define ECR_C_BIT_DTLB_LD_MISS 8
106 #define AUX_EXEC_CTRL 8
112 * Status regs are read-only (build-time) so need not be saved/restored
122 * DSP-related registers
154 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | atafb_iplan2p8.c | 2 * linux/drivers/video/iplan2p8.c -- Low level frame buffer operations for
3 * interleaved bitplanes à la Atari (8
4 * planes, 2 bytes interleave)
20 #define BPL 8
24 /* Copies a 8 plane column from 's', height 'h', to 'd'. */
26 /* This expands a 8 bit color into two longs for two movepl (8 plane)
54 /* odd->odd or even->even */ in atafb_iplan2p8_copyarea()
57 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
58 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
60 memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2); in atafb_iplan2p8_copyarea()
[all …]
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | atafb_iplan2p8.c | 2 * linux/drivers/video/iplan2p8.c -- Low level frame buffer operations for
3 * interleaved bitplanes à la Atari (8
4 * planes, 2 bytes interleave)
20 #define BPL 8
24 /* Copies a 8 plane column from 's', height 'h', to 'd'. */
26 /* This expands a 8 bit color into two longs for two movepl (8 plane)
54 /* odd->odd or even->even */ in atafb_iplan2p8_copyarea()
57 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
58 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
60 memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2); in atafb_iplan2p8_copyarea()
[all …]
|