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/kernel/linux/linux-6.6/drivers/scsi/qla2xxx/
Dqla_devtbl.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
[all …]
/kernel/linux/linux-5.10/drivers/scsi/qla2xxx/
Dqla_devtbl.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/powerpc/fsl/
Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
56 #define TAS5086_CLOCK_RATIO(val) (val << 2)
57 #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
68 #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
56 #define TAS5086_CLOCK_RATIO(val) (val << 2)
57 #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
68 #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/rcar-vin/
Drcar-core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Renesas R-Car VIN
6 * Copyright (C) 2011-2013 Renesas Solutions Corp.
10 * Based on the soc-camera rcar_vin driver
22 #include <media/v4l2-async.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mc.h>
26 #include "rcar-vin.h"
29 * The companion CSI-2 receiver driver (rcar-csi2) is known
31 * pads (pad 1-4). So to translate a pad on the remote
[all …]
/kernel/linux/linux-6.6/drivers/hsi/controllers/
Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 #define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
55 # define SSI_MODE_FRAME 2
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
/kernel/linux/linux-5.10/drivers/hsi/controllers/
Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 #define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
55 # define SSI_MODE_FRAME 2
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/
Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
[all …]
Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
[all …]
/kernel/linux/linux-6.6/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
43 * 2 = Capture output 2.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
47 * 2 = Capture output 2.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
51 * 2 = Capture output 2.
[all …]
/kernel/linux/linux-5.10/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
8 * Output fixed at S32_LE, 2 channel to hw:0,0
15 * Use 2 channel output streams instead of 8 channel.
16 * (8 channel output streams might be good for ASIO type output)
17 * Corrected speaker output, so Front -> Front etc.
36 * Merging with snd-emu10k1 driver.
38 * One stereo channel at 24bit now works.
45 * Some stability problems when unloading the snd-p16v kernel module.
46 * --
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/
Dip22zilog.c1 // SPDX-License-Identifier: GPL-2.0
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
51 #define ZS_WSYNC(channel) do { } while (0) argument
54 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
87 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
90 (UART_ZILOG(PORT)->curregs[REGNUM])
92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
93 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
94 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
[all …]
/kernel/linux/linux-6.6/drivers/tty/serial/
Dip22zilog.c1 // SPDX-License-Identifier: GPL-2.0
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
51 #define ZS_WSYNC(channel) do { } while (0) argument
54 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
87 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
90 (UART_ZILOG(PORT)->curregs[REGNUM])
92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
93 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
94 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/dac/
Dadi,ad5770r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Mircea Caprioru <mircea.caprioru@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD5770R.pdf
21 - adi,ad5770r
26 avdd-supply:
31 iovdd-supply:
35 vref-supply:
41 adi,external-resistor:
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/via/
Dvia_dmablit.h1 /* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
33 #include <linux/dma-mapping.h>
35 #define VIA_NUM_BLIT_ENGINES 2
84 * Channels 2 & 3 don't seem to be implemented in hardware.
87 #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */
88 #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */
89 #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */
90 #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */
92 #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */
[all …]
/kernel/linux/linux-6.6/sound/core/oss/
Drate.c2 * Rate conversion Plug-In
8 * published by the Free Software Foundation; either version 2 of
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
[all …]
/kernel/linux/linux-6.6/sound/pci/ca0106/
Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
34 * playback periods_min=2, periods_max=8
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
[all …]
/kernel/linux/linux-5.10/sound/pci/ca0106/
Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
34 * playback periods_min=2, periods_max=8
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
[all …]
/kernel/linux/linux-5.10/sound/core/oss/
Drate.c2 * Rate conversion Plug-In
8 * published by the Free Software Foundation; either version 2 of
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/
Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/
Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
42 #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
68 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
112 #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)
151 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
152 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
153 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
156 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
157 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
158 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dtlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Dan Murphy <dmurphy@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
28 - const: ti,tlv320adc3140
29 - const: ti,tlv320adc5140
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dtlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
[all …]

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