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/kernel/linux/linux-5.10/arch/nios2/mm/
Dtlb.c22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
38 return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2; in pteaddr_invalid()
47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
53 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2); in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
64 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT)) in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
90 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr); in flush_tlb_one_pid()
[all …]
/kernel/linux/linux-6.6/arch/nios2/mm/
Dtlb.c22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
38 return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2; in pteaddr_invalid()
47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
53 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2); in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
64 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT)) in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
90 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr); in flush_tlb_one_pid()
[all …]
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
27 #define LVL_1_DATA 2
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
[all …]
Dintel.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
61 * Processors which have self-snooping capability can handle conflicting
69 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
101 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
103 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
125 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
126 * - https://kb.vmware.com/s/article/52345
127 * - Microcode revisions observed in the wild
128 * - Release note from 20180108 microcode release
[all …]
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
31 #define LVL_1_DATA 2
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
[all …]
Dintel.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
28 compatible = "arm,armv7-timer";
[all …]
Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/kernel/linux/linux-6.6/arch/openrisc/include/asm/
Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
29 #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
43 #define SPR_CPUCFGR (SPRGROUP_SYS + 2)
71 #define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
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/kernel/linux/linux-5.10/arch/openrisc/include/asm/
Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
29 #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
43 #define SPR_CPUCFGR (SPRGROUP_SYS + 2)
71 #define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dtwofish_glue_3way.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Glue Code for 3-way parallel assembler optimized version of Twofish
25 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
41 u128 ivs[2]; in twofish_dec_blk_cbc_3way()
51 u128_xor(&dst[2], &dst[2], &ivs[1]); in twofish_dec_blk_cbc_3way()
81 dst[2] = src[2]; in twofish_enc_blk_ctr_3way()
88 le128_to_be128(&ctrblks[2], iv); in twofish_enc_blk_ctr_3way()
96 .num_funcs = 2,
97 .fpu_blocks_limit = -1,
109 .num_funcs = 2,
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/kernel/linux/linux-5.10/scripts/tracing/
Dftrace-bisect.sh2 # SPDX-License-Identifier: GPL-2.0
25 # The old (slow) way, for kernels before v5.1.
27 # [old-way] # cat available_filter_functions > ~/full-file
29 # [old-way] *** Note *** this process will take several minutes to update the
30 # [old-way] filters. Setting multiple functions is an O(n^2) operation, and we
31 # [old-way] are dealing with thousands of functions. So go have coffee, talk
32 # [old-way] with your coworkers, read facebook. And eventually, this operation
33 # [old-way] will end.
35 # The new way (using numbers) is an O(n) operation, and usually takes less than a second.
37 # seq `wc -l available_filter_functions | cut -d' ' -f1` > ~/full-file
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/kernel/linux/linux-6.6/scripts/tracing/
Dftrace-bisect.sh2 # SPDX-License-Identifier: GPL-2.0
25 # The old (slow) way, for kernels before v5.1.
27 # [old-way] # cat available_filter_functions > ~/full-file
29 # [old-way] *** Note *** this process will take several minutes to update the
30 # [old-way] filters. Setting multiple functions is an O(n^2) operation, and we
31 # [old-way] are dealing with thousands of functions. So go have coffee, talk
32 # [old-way] with your coworkers, read facebook. And eventually, this operation
33 # [old-way] will end.
35 # The new way (using numbers) is an O(n) operation, and usually takes less than a second.
37 # seq `wc -l available_filter_functions | cut -d' ' -f1` > ~/full-file
[all …]
/kernel/linux/linux-6.6/arch/mips/kernel/
Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
64 #define CP0_DCACHE_TAG_LO $28, 2
68 #define CP0_DCACHE_TAG_HI $29, 2
84 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
107 .align 2
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
[all …]
/kernel/linux/linux-5.10/arch/mips/kernel/
Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
64 #define CP0_DCACHE_TAG_LO $28, 2
68 #define CP0_DCACHE_TAG_HI $29, 2
84 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
107 .align 2
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
[all …]
/kernel/linux/linux-5.10/arch/arm/mm/
Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
51 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
80 return va + (pa_offset >> (32 - PAGE_SHIFT)); in l2_map_va()
[all …]
/kernel/linux/linux-6.6/arch/arm/mm/
Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
51 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
80 return va + (pa_offset >> (32 - PAGE_SHIFT)); in l2_map_va()
[all …]
/kernel/linux/linux-5.10/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
25 * -local_flush_tlb_range( ):
[all …]
/kernel/linux/linux-5.10/arch/powerpc/mm/nohash/
Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
[all …]
/kernel/linux/linux-6.6/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/octeon/
Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
131 CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
183 * Return the L2 Cache way partitioning for a given core.
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
131 CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
183 * Return the L2 Cache way partitioning for a given core.
[all …]
/kernel/linux/linux-6.6/arch/powerpc/mm/nohash/
Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
[all …]
/kernel/linux/linux-5.10/arch/mips/mm/
Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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