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/kernel/linux/linux-6.6/arch/m68k/include/uapi/asm/
Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/uapi/asm/
Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dopp2xxx.h71 #define R1_CLKSEL_USB (4 << 25)
88 #define R2_CLKSEL_USB (2 << 25)
105 #define RB_CLKSEL_USB (1 << 25)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dopp2xxx.h71 #define R1_CLKSEL_USB (4 << 25)
88 #define R2_CLKSEL_USB (2 << 25)
105 #define RB_CLKSEL_USB (1 << 25)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
[all …]
/kernel/linux/linux-6.6/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
[all …]
/kernel/linux/linux-5.10/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
Dnxp,tja11xx.yaml39 typically derived from an external 25MHz crystal. Alternatively,
40 a 50MHz clock signal generated by an external oscillator can be
41 connected to pin REF_CLK. A third option is to connect a 25MHz
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
66 xtal25mhz: xtal25mhz@25M {
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
146 /* TIMER0 runs directly on the 25MHz chrystal */
152 /* TIMER1 runs @ 1MHz */
158 /* TIMER2 runs @ 1MHz */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/arm/
Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
66 xtal25mhz: xtal25mhz@25M {
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmicrel.txt22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_gt_clock_utils.c10 #define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
11 #define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
12 #define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
91 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS in intel_gt_ns_to_pm_interval()
99 val = roundup(val, 25); in intel_gt_ns_to_pm_interval()
/kernel/linux/linux-6.6/drivers/clk/uniphier/
Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-sys.c83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
101 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
102 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/kernel/linux/linux-6.6/drivers/clk/spear/
Dspear1340_clock.c107 #define SPEAR1340_DMA_CLK_ENB 25
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/clk/spear/
Dspear1340_clock.c110 #define SPEAR1340_DMA_CLK_ENB 25
167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/media/tuners/
Dqt1010.c77 { QT1010_RD, 0x23, 0xff }, /* 25 c read */ in qt1010_set_params()
102 #define FREQ1 32000000 /* 32 MHz */ in qt1010_set_params()
103 #define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ in qt1010_set_params()
117 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */ in qt1010_set_params()
118 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */ in qt1010_set_params()
119 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */ in qt1010_set_params()
125 /* 07 - set frequency: 32 MHz scale */ in qt1010_set_params()
128 /* 09 - changes every 8/24 MHz */ in qt1010_set_params()
132 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */ in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
[all …]
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/kernel/linux/linux-6.6/drivers/media/tuners/
Dqt1010.c77 { QT1010_RD, 0x23, 0xff }, /* 25 c read */ in qt1010_set_params()
102 #define FREQ1 32000000 /* 32 MHz */ in qt1010_set_params()
103 #define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ in qt1010_set_params()
117 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */ in qt1010_set_params()
118 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */ in qt1010_set_params()
119 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */ in qt1010_set_params()
125 /* 07 - set frequency: 32 MHz scale */ in qt1010_set_params()
128 /* 09 - changes every 8/24 MHz */ in qt1010_set_params()
132 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */ in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
[all …]
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/
Dice_ptp_consts.h23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
26 823437500, /* 823.4375 MHz PLL */
33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
36 783360000, /* 783.36 MHz */
43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
46 796875000, /* 796.875 MHz */
53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
56 816000000, /* 816 MHz */
63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
66 830078125, /* 830.78125 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
169 { "tdm", NULL, 25 },
/kernel/linux/linux-6.6/drivers/clk/mvebu/
Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
169 { "tdm", NULL, 25 },
/kernel/linux/linux-5.10/drivers/ide/
Dopti621.c76 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */ in opti621_set_pio_mode()
77 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */ in opti621_set_pio_mode()
80 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */ in opti621_set_pio_mode()
81 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */ in opti621_set_pio_mode()
108 printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33); in opti621_set_pio_mode()

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